Inventor

BAROWSKI HARRY

DE54 patents

⚠️ This page may combine multiple inventors who share the name “BAROWSKI HARRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAROWSKI HARRY

IBM

Integrated circuit design changes using through-silicon vias

Soft-bounded hierarchical synthesis

Method and system for data dependent performance increment and power reduction

Write address synchronization in 2 read/1write SRAM arrays

Integrated circuit design changes using through-silicon vias

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Integrated circuit design changes using through-silicon vias

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Integrated circuit design changes using through-silicon vias

Qubit tuning by magnetic fields in superconductors

Formally deriving a minimal clock-gating scheme

Testing content addressable memory and random access memory

Placement clustering-based white space reservation

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Pipelining out-of-order instructions

Cross bar switch structure for highly congested environments

Write address synchronization in 2 read/1write SRAM arrays

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

True complement dynamic circuit and method for combining binary data

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Area sharing between multiple large block synthesis (LBS) blocks

Area sharing between multiple large block synthesis (LBS) blocks

Pipelining out-of-order instructions

De-coupling capacitance placement

De-coupling capacitance placement

Through-silicon via access device for integrated circuits

Through-silicon via access device for integrated circuits

Erasing a partition of an SRAM array with hardware support

Transferring heat through an optical layer of integrated circuitry

Charge recycling between power domains of integrated circuits

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

BAROWSKI HARRY

Integrated circuit package connected to a data transmission medium

Thermal power plane for integrated circuits

Optimized semiconductor packaging in a three-dimensional stack

Multistage, hybrid synthesis processing facilitating integrated circuit layout

Heat sink integrated power delivery and distribution for integrated circuits

Integrated circuit package connected to an optical data transmission medium using a coolant

Optimized semiconductor packaging in a three-dimensional stack

Transferring heat through an optical layer of integrated circuitry

Charge recycling between power domains of integrated circuits

NIGGEMEIER TIM

Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full

Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent

GLOBALFOUNDRIES INC

Techniques for increasing instruction issue rate and reducing latency in an out-of order processor

Transferring heat through an optical layer of integrated circuitry

INT BUSINESS MACHINES CORPORATION

Qubit tuning by magnetic fields in superconductors