Inventor
KEINERT JOACHIM
DE61 patents
⚠️ This page may combine multiple inventors who share the name “KEINERT JOACHIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
29 patentsUS9501603B2Nov 22, 2016
Integrated circuit design changes using through-silicon vias
IBM40 citations98
US6909147B2Jun 21, 2005
Multi-height FinFETS
IBM171 citations98
US7315994B2Jan 1, 2008
Method and device for automated layer generation for double-gate FinFET designs
IBM199 citations96
US6237128B1May 22, 2001
Method and apparatus for enabling parallel layout checking of designing VLSI-chips
IBM22 citations89
US7971171B2Jun 28, 2011
Method and system for electromigration analysis on signal wiring
IBM13 citations84
US10956644B2Mar 23, 2021
Integrated circuit design changes using through-silicon vias
IBM1 citations73
US10242140B2Mar 26, 2019
Layout of large block synthesis blocks in integrated circuits
IBM2 citations73
US10235487B2Mar 19, 2019
Layout of large block synthesis blocks in integrated circuits
IBM2 citations73
US10223491B2Mar 5, 2019
Integrated circuit design changes using through-silicon vias
IBM2 citations73
US9928329B2Mar 27, 2018
Layout of large block synthesis blocks in integrated circuits
IBM3 citations73
US9910948B2Mar 6, 2018
Layout of large block synthesis blocks in integrated circuits
IBM3 citations73
US9569580B2Feb 14, 2017
Integrated circuit design changes using through-silicon vias
IBM2 citations73
US10223489B2Mar 5, 2019
Placement clustering-based white space reservation
IBM2 citations71
US6094812AAug 1, 2000
Dishing avoidance in wide soft metal wires
IBM14 citations69
US7962877B2Jun 14, 2011
Port assignment in hierarchical designs by abstracting macro logic
IBM4 citations63
US4614885ASep 30, 1986
Phase splitter with latch
IBM5 citations60
US10534884B2Jan 14, 2020
Layout of large block synthesis blocks in integrated circuits
IBM0 citations52
US10417366B2Sep 17, 2019
Layout of large block synthesis blocks in integrated circuits
IBM0 citations52
US10366191B2Jul 30, 2019
Layout of large block synthesis blocks in integrated circuits
IBM0 citations52
US10169519B2Jan 1, 2019
Area sharing between multiple large block synthesis (LBS) blocks
IBM0 citations52
US9946830B2Apr 17, 2018
Area sharing between multiple large block synthesis (LBS) blocks
IBM0 citations52
US9684759B2Jun 20, 2017
De-coupling capacitance placement
IBM1 citations52
US9679099B2Jun 13, 2017
De-coupling capacitance placement
IBM1 citations52
US9633928B2Apr 25, 2017
Through-silicon via access device for integrated circuits
IBM0 citations52
US9412682B2Aug 9, 2016
Through-silicon via access device for integrated circuits
IBM1 citations52
US8984314B2Mar 17, 2015
Charge recycling between power domains of integrated circuits
IBM0 citations51
US10579773B2Mar 3, 2020
Layouting of interconnect lines in integrated circuits
IBM0 citations50
US10417377B2Sep 17, 2019
Layouting of interconnect lines in integrated circuits
IBM0 citations50
US10013521B2Jul 3, 2018
Layouting of interconnect lines in integrated circuits
IBM0 citations50
FRAUNHOFER GES FORSCHUNG
13 patentsUS8811811B1Aug 19, 2014
Camera system and method for generating high-quality HDR images or videos
FRAUNHOFER GES FORSCHUNG14 citations81
US12033339B2Jul 9, 2024
Localization of elements in the space
FRAUNHOFER GES FORSCHUNG2 citations71
US10803624B2Oct 13, 2020
Apparatus for providing calibration data, camera system and method for obtaining calibration data
FRAUNHOFER GES FORSCHUNG5 citations71
US11699263B2Jul 11, 2023
Apparatus, method and computer program for rendering a visual scene
FRAUNHOFER GES FORSCHUNG5 citations69
US11006133B2May 11, 2021
Image compression technique
FRAUNHOFER GES FORSCHUNG2 citations68
US10721470B2Jul 21, 2020
Compression of a raw image
FRAUNHOFER GES FORSCHUNG2 citations62
US11954874B2Apr 9, 2024
Localization of elements in the space
FRAUNHOFER GES FORSCHUNG0 citations61
US11546614B1Jan 3, 2023
Encoder and decoder for encoding and decoding images
FRAUNHOFER GES FORSCHUNG2 citations61
US12149744B2Nov 19, 2024
Apparatus and method for encoding and decoding a sequence of pictures using a buffered transform signal approximation
FRAUNHOFER GES FORSCHUNG0 citations59
US12132934B2Oct 29, 2024
Operation method of electronic device for encoding and decoding a sequence of pictures using a buffered transform signal approximation
FRAUNHOFER GES FORSCHUNG0 citations59
US11736731B2Aug 22, 2023
Encoding and decoding a sequence of pictures
FRAUNHOFER GES FORSCHUNG0 citations59
US11457232B2Sep 27, 2022
Bit-plane encoder and decoder
FRAUNHOFER GES FORSCHUNG0 citations59
US11438617B2Sep 6, 2022
Transform coefficients encoder and decoder
FRAUNHOFER GES FORSCHUNG0 citations59
KEINERT JOACHIM
6 patentsUS8418110B2Apr 9, 2013
Using port obscurity factors to improve routing
KEINERT JOACHIM12 citations83
US8495547B2Jul 23, 2013
Providing secondary power pins in integrated circuit design
KEINERT JOACHIM15 citations82
US8762919B2Jun 24, 2014
Circuit macro placement using macro aspect ratio based on ports
KEINERT JOACHIM2 citations62
US8429584B2Apr 23, 2013
Method, electronic design automation tool, computer program product, and data processing program for creating a layout for design representation of an electronic circuit and corresponding port for an electronic circuit
KEINERT JOACHIM3 citations62
US8495551B2Jul 23, 2013
Shaping ports in integrated circuit design
KEINERT JOACHIM1 citations51
US8276105B2Sep 25, 2012
Automatic positioning of gate array circuits in an integrated circuit design
KEINERT JOACHIM1 citations51
HOPKINS JEREMY T
1 patentBAROWSKI HARRY
1 patentShowing the top 50 of 61 patents by PatentIndex Score.