Inventor

PHAN ANH

US45 patents

⚠️ This page may combine multiple inventors who share the name “PHAN ANH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PHAN ANH

INTEL CORP

Backside contacts for semiconductor devices

Stacked forksheet transistors

Stacked nanowire transistor structure with different channel geometries for stress

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors having device strata with different channel widths

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Stacked transistors with different gate lengths in different device strata

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Stacked transistor structures with asymmetrical terminal interconnects

Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

Leave-behind protective layer having secondary purpose

Vertical diode in stacked transistor architecture

Transistors stacked on front-end p-type transistors

Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor

Sideways vias in isolation areas to contact interior layers in stacked devices

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Isolation wall stressor structures to improve channel stress and their methods of fabrication

Leave-behind protective layer having secondary purpose

Sideways vias in isolation areas to contact interior layers in stacked devices

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process for forming such

Metallization structures for stacked device connectivity and their methods of fabrication

Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

Forming an oxide volume within a fin

Vertically stacked transistor devices with isolation wall structures containing an electrical conductor

Stacked source-drain-gate connection and process for forming such

Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

Stacked trigate transistors with dielectric isolation between first and second semiconductor fins

Stacked transistors with dielectric between channels of different device strata

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Metallization structures for stacked device connectivity and their methods of fabrication

Isolation wall stressor structures to improve channel stress and their methods of fabrication

Backside contacts for semiconductor devices

Self-aligned local interconnects

Pedestal fin structure for stacked transistor integration

Epitaxial layer with substantially parallel sides

Sidewall interconnect metallization structures for integrated circuit devices

Three dimensional integrated circuits with stacked transistors

Stacked transistor architecture including nanowire or nanoribbon thin film transistors

APPLE INC

Parking event detection and location estimation

LILAK AARON D

CMOS architecture with thermally stable silicide gate workfunction metal