Inventor

LI XIA

US337 patents

⚠️ This page may combine multiple inventors who share the name “LI XIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI XIA

QUALCOMM INC

Three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, and related methods and systems

Magnetic tunnel junction cell including multiple vertical magnetic domains

Method of forming a magnetic tunnel junction structure

Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications

Self-compensation of stray field of perpendicular magnetic elements

Multi-bit spin torque transfer magnetoresistive random access memory with sub-arrays

Magnetic tunnel junction and method for fabricating a magnetic tunnel junction

Logic finFET high-K/conductive gate embedded multiple time programmable flash memory

MRAM integration techniques for technology scaling

MTJ structure and integration scheme

MRAM device and integration techniques compatible with logic integration

Magnetic tunnel junction device with separate read and write paths

Method of forming a magnetic tunnel junction device

Semiconductor device implemented with buried rails

Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance to enhance transistor imbalance for improved PUF output reproducibility

Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits

Non-volative (NV) memory (NVM) matrix circuits employing NVM matrix circuits for performing matrix computations

Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors

Thermally enhanced substrate

Complementary metal-oxide semiconductor (CMOS) integration with compound semiconductor devices

Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path

Planar double gate semiconductor device

Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds

LI XIA

Cabinet

Cabinet

Cabinet

Cabinet

Method of forming a magnetic tunnel junction structure

MTJ structure and integration scheme

MRAM device and integration techniques compatible with logic integration

Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions

Wireless magnetic car charger

Car phone holder

MC10 INC

Flexible temperature sensor including conformable electronics

Electronic device having antenna

Electronic device having antenna

CHARTERED SEMICONDUCTOR MFG

Method of fabricating T-shaped recessed polysilicon gate transistors

Method of fabricating T-shaped recessed polysilicon gate transistors

MONELL CHEMICAL SENSES CENTRE

Taste receptors of the T1R family from domestic dog

Taste receptors of the T1R family from domestic cat

APPLE INC

Display with embedded pixel driver chips

Stacked hybrid micro LED pixel architecture

GEN ELECTRIC

Deep learning for arterial analysis and assessment

ZHU XIAOCHUN

Strain induced reduction of switching current in spin-transfer torque switching devices

GE LIANG

Constraint optimization of sub-net level routing in asic design

KIM JUNG PILL

OTP cell with reversed MTJ connection

RAO HARI M

Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

KANG SEUNG H

Two mask MTJ integration for STT MRAM

LEE KANGHO

Magnetic tunnel junction device and fabrication