Inventor
TSUI BING-YUE
TW24 patents
⚠️ This page may combine multiple inventors who share the name “TSUI BING-YUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IND TECH RES INST
9 patentsUS5891799AApr 6, 1999
Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
IND TECH RES INST218 citations98
US6225211B1May 1, 2001
Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits
IND TECH RES INST72 citations96
US6759305B2Jul 6, 2004
Method for increasing the capacity of an integrated circuit device
IND TECH RES INST26 citations92
US6566752B2May 20, 2003
Bonding pad and method for manufacturing it
IND TECH RES INST16 citations92
US6303419B1Oct 16, 2001
Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer
IND TECH RES INST22 citations92
US5959309ASep 28, 1999
Sensor to monitor plasma induced charging damage
IND TECH RES INST39 citations92
US5792699AAug 11, 1998
Method for reduction of reverse short channel effect in MOSFET
IND TECH RES INST48 citations92
US5702566ADec 30, 1997
Conductive photoresist to mitigate antenna effect
IND TECH RES INST30 citations92
US6426555B1Jul 30, 2002
Bonding pad and method for manufacturing it
IND TECH RES INST15 citations83
NATIONAL YANG MING CHIAO TUNG UNIV
5 patentsUS12256559B2Mar 18, 2025
Source-body self-aligned method of a vertical double diffused metal oxide semiconductor field effect transistor
NATIONAL YANG MING CHIAO TUNG UNIV1 citations59
US12463039B2Nov 4, 2025
Method for reducing parasitic junction field effect transistor resistance
NATIONAL YANG MING CHIAO TUNG UNIV0 citations47
US12507436B2Dec 23, 2025
Gate fabrication method of an U-metal-oxide-semiconductor field-effect transistor and trench gate structure formed thereof
NATIONAL YANG MING CHIAO TUNG UNIV0 citations45
US12588264B2Mar 24, 2026
Three-dimensional source contact structure and fabrication process method of making the same
NATIONAL YANG MING CHIAO TUNG UNIV0 citations41
US12408372B2Sep 2, 2025
Process method for fabricating a three-dimensional source contact structure
NATIONAL YANG MING CHIAO TUNG UNIV0 citations41
EPISIL TECHNOLOGIES INC
4 patentsUS6489204B1Dec 3, 2002
Save MOS device
EPISIL TECHNOLOGIES INC93 citations97
US7294550B2Nov 13, 2007
Method of fabricating metal oxide semiconductor device
EPISIL TECHNOLOGIES INC3 citations62
US7517759B2Apr 14, 2009
Method of fabricating metal oxide semiconductor device
EPISIL TECHNOLOGIES INC0 citations51
US7391079B2Jun 24, 2008
Metal oxide semiconductor device
EPISIL TECHNOLOGIES INC0 citations51
UNIV NAT CHIAO TUNG
2 patentsUNIV NATIONAL CHIAO TUNG
2 patentsUS11538920B2Dec 27, 2022
Method for increasing an oxide thickness at trench corner of an U-shaped gate metal-oxide-semiconductor field-effect transistor
UNIV NATIONAL CHIAO TUNG0 citations43
US11342417B2May 24, 2022
Semiconductor structure of trench transistors and manufacturing method thereof
UNIV NATIONAL CHIAO TUNG0 citations43