Inventor

CAI XIUYU

US172 patents

⚠️ This page may combine multiple inventors who share the name “CAI XIUYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAI XIUYU

GLOBALFOUNDRIES INC

Methods of removing dummy fin structures when forming finFET devices

Topological method to build self-aligned MTJ without a mask

Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance

Methods of forming replacement spacer structures on semiconductor devices

FinFet integrated circuits with uniform fin height and methods for fabricating the same

Methods of forming isolation material on FinFET semiconductor devices and the resulting devices

Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

Methods of increasing space for contact elements by using a sacrificial liner and the resulting device

Methods of forming bulk FinFET devices by performing a recessing process on liner materials to define different fin heights and FinFET devices with such recessed liner materials

Methods of forming a protection layer on a semiconductor device and the resulting device

Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices

Dual-strained nanowire and FinFET devices with dielectric isolation

Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

Semiconductor device with low-K spacers

Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device

Methods of forming MIS contact structures for semiconductor devices and the resulting devices

Methods of forming fins for finFET semiconductor devices and the selective removal of such fins

FinFET semiconductor device with a recessed liner that defines a fin height of the FinFet device

Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices

Integrated circuits with improved gate uniformity and methods for fabricating same

Methods of forming semiconductor device with self-aligned contact elements and the resulting devices

Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device

ST MICROELECTRONICS INC

Multi-channel gate-all-around FET

Multi-channel gate-all-around FET

FinFETs having strained channels, and methods of fabricating finFETs having strained channels

Methods for forming vertical and sharp junctions in finFET structures

LDMOS FinFET device using a long channel region and method of manufacture

FinFETs and techniques for controlling source and drain junction profiles in finFETs

Hetero-channel FinFET

Method of forming a reduced resistance fin structure

LDMOS finFET device and method of manufacture using a trench confined epitaxial growth process

Method for making semiconductor device with filled gate line end recesses

Large area contacts for small transistors

Method for making a semiconductor device with sidewall spacers for confining epitaxial growth

Method for making semiconductor device with different fin sets

Method for making semiconductor device with isolation pillars between adjacent semiconductor fins

Semiconductor device including vertically spaced semiconductor channel structures and related methods

IBM

Method and structure of forming controllable unmerged epitaxial material

Replacement low-k spacer

FinFET including tunable fin height and tunable fin width ratio

Series resistance reduction in vertically stacked silicon nanowire transistors

High doped III-V source/drain junctions for field effect transistors

Forming reliable contacts on tight semiconductor pitch

Gate structure cut after formation of epitaxial active regions

Field effect transistor device spacers

Prevention of fin erosion for semiconductor devices

XIE RUILONG

Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation

Methods of forming semiconductor devices with self-aligned contacts and the resulting devices

CAI XIUYU

Methods of forming CMOS semiconductor devices

ILLUMINA INC

Two-filter light detection devices and methods related to same