Inventor

BARNS CHRIS E

US36 patents

⚠️ This page may combine multiple inventors who share the name “BARNS CHRIS E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARNS CHRIS E

INTEL CORP

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Methods for integrating replacement metal gate structures

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Integrating n-type and p-type metal gate transistors

Method of forming a selectively converted inter-layer dielectric using a porogen material

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Integrating n-type and p-type metal gate transistors

Planarizing a semiconductor structure to form replacement metal gates

integrating n-type and P-type metal gate transistors

Integrating n-type and p-type metal gate transistors

Method for making a semiconductor device that includes a metal gate electrode

Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Polysilicon opening polish

Etch stop and hard mask film property matching to enable improved replacement metal gate process

Poly open polish process

Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction

Selectively converted inter-layer dielectric

Sacrificial dielectric planarization layer

Facilitating removal of sacrificial layers via implantation to form replacement metal gates

Preventing silicide formation at the gate electrode in a replacement metal gate technology

Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

Through-pad slurry delivery for chemical-mechanical polish

Polysilicon opening polish

Sacrificial dielectric planarization layer

CMOS device with metal and silicide gate electrodes and a method for making it

Selectively converted inter-layer dielectric

Introducing nanotubes in trenches and structures formed thereby

Semiconductor substrate polishing methods and equipment

NASA

Multiple axis reticle

INTEGRATED PROCESS EQUIPMENT C

Semiconductor wafer polishing apparatus with a flexible carrier plate

KAVALIEROS JACK

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

SPEEDFAM IPEC CORP

Work piece wand and method for processing work pieces using a work piece handling wand