Inventor

XIE RUILONG

US1,264 patents

⚠️ This page may combine multiple inventors who share the name “XIE RUILONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XIE RUILONG

GLOBALFOUNDRIES INC

Uniformity tuning of variable-height features formed in trenches

Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Silicide protection during contact metallization and resulting semiconductor structures

Structures and SRAM bit cells with a buried cross-couple interconnect

Work function metal patterning for N-P space between active nanostructures

Nanosheet field-effect transistors including a two-dimensional semiconducting material

Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming

Integrated circuit structure incorporating stacked field effect transistors

Complementary FETs with wrap around contacts and method of forming same

Integrated circuit structure incorporating multiple gate-all-around field effect transistors having different drive currents and method

Nanosheet field-effect transistor with full dielectric isolation

Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method

Inner spacer formation for nanosheet field-effect transistors with tall suspensions

Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device

Self-aligned wrap-around contacts for nanosheet devices

Method and structure of forming self-aligned RMG gate for VFET

Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques

Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Methods of forming lateral and vertical FinFET devices and the resulting product

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

Methods of removing dummy fin structures when forming finFET devices

Vertically stacked complementary-FET device with independent gate control

Insulated epitaxial structures in nanosheet complementary field effect transistors

Air-gap gate sidewall spacer and method

Methods of forming an isolated nano-sheet transistor device and the resulting device

Insulative structure with diffusion break integral with isolation layer and methods to form same

Inner spacer formation in a nanosheet field-effect transistor

Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices

Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures

Gate and source/drain contact structures positioned above an active region of a transistor device

Method to form low resistance contact

Nanosheet transistor with uniform effective gate length

Wrap-around contacts formed with multiple silicide layers

Stacked nanosheet field-effect transistor with air gap spacers

Method of forming vertical field effect transistors with different gate lengths and a resulting structure

Gate contact structure positioned above an active region of a transistor device

IBM

Inner spacer for nanosheet transistors

Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain

Fabrication of vertical field effect transistor structure with controlled gate length

Etch stop for airgap protection

MOSFET with asymmetric self-aligned contact

Method and structure of forming controllable unmerged epitaxial material

Stacked field effect transistors with reduced coupling effect

Self-aligned gate isolation with asymmetric cut placement

Integration of air spacer with self-aligned contact in transistor

Nanosheet FET with box isolation on substrate

ST MICROELECTRONICS INC

Multi-channel gate-all-around FET

XIE RUILONG

Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices

GLOBALFOUNDRIES US INC

Gate-all-around field effect transistors with robust inner spacers and methods