Inventor

KIM CHANGKYU

US32 patents

⚠️ This page may combine multiple inventors who share the name “KIM CHANGKYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM CHANGKYU

INTEL CORP

Instruction and logic to provide pushing buffer copy and store functionality

Gather and scatter operations in multi-level memory hierarchy

Vector instructions to enable efficient synchronization and parallel reduction operations

Search unit to accelerate variable length compression/decompression

Gather and scatter operations in multi-level memory hierarchy

Instruction and logic to provide pushing buffer copy and store functionality

Texture unit for general purpose computing

LG ELECTRONICS INC

Linear compressor and refrigerator including a linear compressor

Gripper

Linear compressor

Linear compressor and refrigerator cycle including a linear compressor

Linear compressor and a linear motor for a linear compressor

Linear compressor

Linear compressor with sound dampening gaskets

HUGHES CHRISTOPHER J

Gather and scatter operations in multi-level memory hierarchy

Gather and scatter operations in multi-level memory hierarchy

Method and system to increase concurrency and control replication in a multi-core cache hierarchy

KIM CHANGKYU

Methods and systems to determine conservative view cell occlusion

Detection of streaming data in cache

Virtual row buffers for use with random access memory

LEE VICTOR W

Texture unit for general purpose computing

Grouping pixels to be textured

UNIV TEXAS

Non-uniform cache apparatus, systems, and methods

BURGER DOUGLAS C

Dynamically composing processor cores to form logical processors

SMELYANSKIY MIKHAIL

Vector instructions to enable efficient synchronization and parallel reduction operations

KIM DAEHYUN

Method and apparatus for stream buffer management instructions

LEE JAEKYU

Semiconductor memory devices

SAMSUNG ELECTRONICS CO LTD

Three-dimensional semiconductor memory device

LI WENLONG

Shared cache memories for multi-core processors

SATISH NADATHUR RAJAGOPALAN

Cache and/or socket sensitive multi-processor cores breadth-first traversal

CHHUGANI JATIN

Method of decreasing a total computation time for a visual simulation loop in a virtual world application

SEWALL JASON D

Parallel operation in B+ trees