Inventor

LILLY BRIAN P

US40 patents

⚠️ This page may combine multiple inventors who share the name “LILLY BRIAN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LILLY BRIAN P

APPLE INC

Combining write buffer with dynamically adjustable flush metrics

Scalable cache coherency protocol

Combined single error correction/device kill detection code

Mechanism for sharing private caches in a SoC

Cache policies for uncacheable memory requests

Request ordering in a cache

Coprocessor context priority

Least recently used mechanism for cache line eviction from a cache memory

Prefetching across page boundaries in hierarchically cached processors

Methods for cache line eviction

Flush engine

Scalable cache coherency protocol

Scalable cache coherency protocol

Scalable cache coherency protocol

Cache pre-fetch merge in pending request buffer

Latency reduction for cache coherent bus-based cache

Integrated circuit with multiported memory supercell and data path switching circuitry

Latency reduction for cache coherent bus-based cache

Latency reduction for cache coherent bus-based cache

Request ordering in a cache

Delaying cache data array updates

Coprocessor context priority

Variable hit latency cache

Method and apparatus for determining tunable parameters to use in power and performance management

Parallel coherence and memory cache processing pipelines

L2 cache retention mode

Combining write buffer with dynamically adjustable flush metrics

Least recently used mechanism for cache line eviction from a cache memory

Selective victimization in a multi-level cache hierarchy

Method and apparatus for ensuring real-time snoop latency

Managing fast to slow links in a bus fabric

Selective cache way-group power down

LAMPERT DAVID L

Range of motion machine and method and adjustable crank

Range of motion machine and method and adjustable crank

Range of motion machine and method and adjustable crank

LILLY BRIAN P

QoS management in the L2 cache

Critical word forwarding with adaptive prediction

Combined single error correction/device kill detection code

KANNAN HARI S

Coordinated prefetching based on training in hierarchically cached processors

BISWAS SUKALPA

Multiple critical word bypassing in a memory controller