Inventor

WILLIAMS III GERARD R

US48 patents

⚠️ This page may combine multiple inventors who share the name “WILLIAMS III GERARD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILLIAMS III GERARD R

APPLE INC

Trust zone support in system on a chip having security enclave processor

Load/store dependency predictor optimization for replayed loads

Access permissions modification

Unified prefetch circuit for multi-level caches

Computation engine that operates in matrix and vector modes

Unified prefetch circuit for multi-level caches

Systems and methods for performing memory compression

Processor including multiple dissimilar processor cores

Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

Access map-pattern match based prefetch unit for a processor

Multi-core processor instruction throttling

Multi-level dispatch for a superscalar processor

Systems and methods for coherent power management

Computation engine with extract instructions to minimize memory access

Systems and methods for coherent power management

Processor including multiple dissimilar processor cores

Processor and method for implementing barrier operation using speculative and architectural color values

Usefulness indication for indirect branch prediction training

Mechanism for sharing private caches in a SoC

IT instruction pre-decode

Cache policies for uncacheable memory requests

Scalable system on a chip

Least recently used mechanism for cache line eviction from a cache memory

Systems and methods for coherent power management

Systems and methods for coherent power management

Flush engine

Hashing with soft memory folding

Computation engine that operates in matrix and vector modes

Systems and methods for performing memory compression

Reduced power operation using stored capacitor energy

Ensuring transactional ordering in I/O agent

Hashing with soft memory folding

Reduced power operation using stored capacitor energy

Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage

Marking valid return targets

Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

Least recently used mechanism for cache line eviction from a cache memory

Persistent relocatable reset vector for processor

Global maintenance command protocol in a cache coherent system

MEIER STEPHAN G

Load-store dependency predictor PC hashing

Load-store dependency predictor content management

KELLER JAMES B

Zero cycle move

Optimizing register initialization operations

WILLIAMS III GERARD R

Converting memory accesses near barriers into prefetches

Zero cycle load

KANNAN HARI S

Coordinated prefetching based on training in hierarchically cached processors

GUPTA SANDEEP

Instruction set architecture mode dependent sub-size access of register with associated status indication

KOUNTANIS IAN D

Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries