Inventor

KANAPATHIPILLAI PRADEEP

US30 patents

⚠️ This page may combine multiple inventors who share the name “KANAPATHIPILLAI PRADEEP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANAPATHIPILLAI PRADEEP

APPLE INC

Load/store dependency predictor optimization for replayed loads

Access permissions modification

Completing load and store instructions in a weakly-ordered memory model

Out of order store commit

Unified prefetch circuit for multi-level caches

Unified prefetch circuit for multi-level caches

Reducing latency for pointer chasing loads

Load ordering in a weakly-ordered processor

Cache policies for uncacheable memory requests

Load-store unit with banked queue

Prefetching across page boundaries in hierarchically cached processors

Execution unit power management

Translation lookaside buffer invalidation by range

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies

DSB operation with excluded region

DSB operation with excluded region

Delaying cache data array updates

Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

Unified address translation

Architected state retention for a frequent operating state switching processor

Hierarchical clock control using hysterisis and threshold management

Hardware compression and decompression engine

Mechanism for allowing speculative execution of loads beyond a wait for event instruction

QUALCOMM INC

Dynamic voltage and frequency scaling (DVFS) within processor clusters

Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip

Latency management in synchronization events

Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods

KANNAN HARI S

Coordinated prefetching based on training in hierarchically cached processors

Efficient handling of misaligned loads and stores

BEAUMONT-SMITH ANDREW J

Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies