Inventor
YILDIZ MEHMET CAN
US30 patents
⚠️ This page may combine multiple inventors who share the name “YILDIZ MEHMET CAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
29 patentsUS11734485B1Aug 22, 2023
Routing congestion based on fractional via cost and via density
CADENCE DESIGN SYSTEMS INC7 citations85
US10997352B1May 4, 2021
Routing congestion based on layer-assigned net and placement blockage
CADENCE DESIGN SYSTEMS INC9 citations85
US10963617B1Mar 30, 2021
Modifying route topology to fix clock tree violations
CADENCE DESIGN SYSTEMS INC11 citations85
US10460066B1Oct 29, 2019
Routing framework to resolve single-entry constraint violations for integrated circuit designs
CADENCE DESIGN SYSTEMS INC9 citations84
US10460063B1Oct 29, 2019
Integrated circuit routing based on enhanced topology
CADENCE DESIGN SYSTEMS INC2 citations73
US10460064B1Oct 29, 2019
Partition-aware grid graph based hierarchical global routing
CADENCE DESIGN SYSTEMS INC4 citations73
US10102328B1Oct 16, 2018
System and method for constructing spanning trees
CADENCE DESIGN SYSTEMS INC5 citations73
US11132489B1Sep 28, 2021
Layer assignment based on wirelength threshold
CADENCE DESIGN SYSTEMS INC3 citations72
US11030377B1Jun 8, 2021
Routing based on pin placement within routing blockage
CADENCE DESIGN SYSTEMS INC4 citations72
US10885257B1Jan 5, 2021
Routing congestion based on via spacing and pin density
CADENCE DESIGN SYSTEMS INC6 citations72
US10706201B1Jul 7, 2020
Circuit design routing using multi-panel track assignment
CADENCE DESIGN SYSTEMS INC6 citations72
US10685164B1Jun 16, 2020
Circuit design routing based on parallel run length rules
CADENCE DESIGN SYSTEMS INC2 citations72
US10289795B1May 14, 2019
Routing tree topology generation
CADENCE DESIGN SYSTEMS INC4 citations72
US10289792B1May 14, 2019
Systems and methods for clustering pins for power
CADENCE DESIGN SYSTEMS INC4 citations72
US12216977B1Feb 4, 2025
Maximum turn constraint for routing of integrated circuit designs
CADENCE DESIGN SYSTEMS INC2 citations69
US12393760B1Aug 19, 2025
Wire density-aware layer assignment
CADENCE DESIGN SYSTEMS INC1 citations63
US11928500B1Mar 12, 2024
Multi-threaded network routing based on partitioning
CADENCE DESIGN SYSTEMS INC1 citations62
US11030378B1Jun 8, 2021
Track assignment by dynamic programming
CADENCE DESIGN SYSTEMS INC1 citations62
US12505274B1Dec 23, 2025
Detecting and modeling via during global routing
CADENCE DESIGN SYSTEMS INC0 citations60
US12536361B1Jan 27, 2026
Network assignment based on non-default design rules
CADENCE DESIGN SYSTEMS INC0 citations51
US12423499B1Sep 23, 2025
Resistance and capacitance aware preferred layer trimming
CADENCE DESIGN SYSTEMS INC0 citations51
US12393763B1Aug 19, 2025
Timing-based layer assignment
CADENCE DESIGN SYSTEMS INC0 citations51
US11675955B1Jun 13, 2023
Routing using rule-based blockage extension
CADENCE DESIGN SYSTEMS INC0 citations51
US11080457B1Aug 3, 2021
Layer assignment and routing based on resistance or capacitance characteristic
CADENCE DESIGN SYSTEMS INC0 citations51
US12505277B1Dec 23, 2025
Cell-based pin access location generation
CADENCE DESIGN SYSTEMS INC0 citations50
US11461530B1Oct 4, 2022
Circuit design routing based on routing demand adjustment
CADENCE DESIGN SYSTEMS INC0 citations50
US12585858B1Mar 24, 2026
Grid cell routing capacity adjustment based on pin density
CADENCE DESIGN SYSTEMS INC0 citations49
US12314651B1May 27, 2025
Zigzag detection and handling for integrated circuit design
CADENCE DESIGN SYSTEMS INC0 citations47
US10460065B1Oct 29, 2019
Routing topology generation using spine-like tree structure
CADENCE DESIGN SYSTEMS INC0 citations41