Inventor

LIANG YUE

CN54 patents

⚠️ This page may combine multiple inventors who share the name “LIANG YUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIANG YUE

IBM

Semiconductor device having dual metal gates and method of manufacture

Method of providing threshold voltage adjustment through gate dielectric stack modification

Dual metal and dual dielectric integration for metal high-k FETs

Dummy gate interconnect for semiconductor device

Tucked active region without dummy poly for performance boost and variation reduction

MOS having a sic/sige alloy stack

Asymmetric semiconductor devices and method of fabricating

Semiconductor process temperature optimization

Work function adjustment by carbon implant in semiconductor devices including gate structure

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

Post-gate shallow trench isolation structure formation

Programmable FETs using Vt-shift effect and methods of manufacture

Method and structure for pFET junction profile with SiGe channel

OFS FITEL LLC

Splicing optical fiber cable using a mass fusion splicer having a pitch different from cable pitch

Apparatus for alignment of a multicore fiber in a multifiber connector and method of using same

Splicing twisted multiple core optical fibers

Light cover or hood for live optical fiber identifier tool

Ribbon transition tool

Methods and apparatus for aligning and splicing optical fibers

Methods and apparatus for aligning and splicing optical fibers

Live optical fiber identifier tool

Routing of multicore optical fibers in data networks

XIAOMI INC

Firmware refreshing method and device

Method and apparatus for monitoring status of terminal compressor

Method and apparatus for accessing network

Method and apparatus for controlling turn-on and turn-off of smart socket

AAC TECHNOLOGIES PTE LTD

MIMO antenna and terminal

Multi-antenna system and mobile terminal

Transmission line cable including an unbendable superimposed layer part and a bendable non-superimposed layer part

Antenna system and electronic device

CHUDZIK MICHAEL P

Method and structure for gate height scaling with high-k/metal gate technology

Method and structure for gate height scaling with high-k/metal gate technology

Dual metal and dual dielectric integration for metal high-K FETs

CHIDAMBARRAO DURESETI

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

CMOS having a SiC/SiGe alloy stack

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

YU XIAOJUN

Tucked active region without dummy poly for performance boost and variation reduction

Post-gate shallow trench isolation structure formation

Selective partial gate stack for improved device isolation

LIANG YUE

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

Work function adjustment by carbon implant in semiconductor devices including gate structure

UNIV LELAND STANFORD JUNIOR

Negative differential resistance devices and approaches therefor

GREENE BRIAN J

Threshold voltage adjustment through gate dielectric stack modification

BRADLEY KELVIN B

Apparatus for alignment of a multicore fiber in a multifiber connector and method of using same

RIM KERN

Method and structure for pFET junction profile with SiGe channel

QUALCOMM INC

Temperature and ultrasonic sensor fusion for biometric sensing

BRODSKY MARYJANE

Threshold voltage adjustment for thin body MOSFETs

APPLE INC

Accessory device with concealed internal buttons features

GLOBALFOUNDRIES INC

Tucked active region without dummy poly for performance boost and variation reduction

CARTIER EDUARD A

Programmable FETs using Vt-shift effect and methods of manufacture