Inventor

KOTRA JAGADISH B

US41 patents

⚠️ This page may combine multiple inventors who share the name “KOTRA JAGADISH B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOTRA JAGADISH B

ADVANCED MICRO DEVICES INC

Preserving memory ordering between offloaded instructions and non-offloaded instructions

Processor-guided execution of offloaded instructions using fixed function operations

Method and apparatus for virtualizing the micro-op cache

Method and apparatus for virtualizing the micro-op cache

Processor-guided execution of offloaded instructions using fixed function operations

Implementing a micro-operation cache with compaction

Data compression and encryption based on translation lookaside buffer evictions

Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs

Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host

Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems

Method and apparatus for recovering regular access performance in fine-grained DRAM

Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems

Bypassing cache directory lookups for processing-in-memory instructions

Offloading computations from a processor to remote execution logic

Methods for configuring span of control under varying temperature

Storing indications of cleared cache lines

Preserving memory ordering between offloaded instructions and non-offloaded instructions

Systems and methods for branch misprediction aware cache prefetcher training

Implementing a micro-operation cache with compaction

Accessing a cache based on an address translation buffer result

Speculative dram request enabling and disabling

Method and apparatus for reducing the latency of long latency memory requests

Hardware-assisted dynamic random access memory (DRAM) row merging

Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs

Temporal link encoding

Techniques to improve translation lookaside buffer reach by leveraging idle resources

Method and apparatus for recovering regular access performance in fine-grained DRAM

Method and apparatus for quantization and dequantization of neural network input and output data using processing-in-memory

Tag and data configuration for fine-grained cache memory

Arbitrating atomic memory operations

Data as compute

Method and apparatus to expedite system services using processing-in-memory (PIM)

Data compression and decompression for processing in memory

Adaptive cache management based on programming model information

Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

Managing a cache using per memory region reuse distance estimation

Dispatch bandwidth of memory-centric requests by bypassing storage array address checking

Method and apparatus for a dram cache tag prefetcher

Leveraging processing in memory registers as victim buffers

Filtering micro-operations for a micro-operation cache in a processor

BOEHLER OLIVIER

Intelligent command prediction