Inventor

ROY PRADIP K

US73 patents

⚠️ This page may combine multiple inventors who share the name “ROY PRADIP K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROY PRADIP K

LUCENT TECHNOLOGIES INC

Use of SiD4 for deposition of ultra thin and controllable oxides

System and method for determining near--surface lifetimes and the tunneling field of a dielectric in a semiconductor

Method of passivating copper interconnects in a semiconductor

Method for forming a high quality ultrathin gate oxide layer

Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology

DRAM capacitor including Cu plug and Ta barrier and method of forming

Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate

Barrier layer treatments for tungsten plug

In-line non-contact depletion capacitance measurement method and apparatus

Non-contact method for determining the presence of a contaminant in a semiconductor device

Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device

Process for deuterium passivation and hot carrier immunity

AGERE SYST GUARDIAN CORP

System and method for forming a uniform thin gate oxide layer

Layered dielectric film structure suitable for gate dielectric application in sub-0.25 μm technologies

Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof

Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same

System and method for forming a uniform thin gate oxide layer

Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique

NEXPLANAR CORP

Customized polishing pads for CMP and methods of fabrication and use thereof

Customized polishing pads for CMP and methods of fabrication and use thereof

Customized polish pads for chemical mechanical planarization

Customized polish pads for chemical mechanical planarization

Customized polish pads for chemical mechanical planarization

Customized polishing pads for CMP and methods of fabrication and use thereof

AT & T BELL LAB

Growth-modified thermal oxidation for thin oxides

Forming a device dielectric on a deposited semiconductor having sub-layers

Silicide formation on polysilicon

Method of making thin film transistors including recrystallization and high pressure oxidation

Semiconductor device with low defect density oxide

Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer

GEN FOODS CORP

Process of preparing gasified candy

Apparatus and process for the preparation of gasified confectionaries by pressurized injection molding

Gasified candy having a predetermined shape

AT & T CORP

Multiple layer tungsten deposition process

Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer

AMERICAN TELEPHONE & TELEGRAPH

Fabricating a semiconductor device with low defect density oxide

Multilayering process for stress accommodation in deposited polysilicon

ROY PRADIP K

Customized polishing pads for CMP and methods of fabrication and use thereof

Customized polishing pads for CMP and methods of fabrication and use thereof

DEOPURA MANISH

Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs

Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs

AGERE SYSTEMS INC

Non-contact method for determining quality of semiconductor dielectrics

Composite polishing pads for chemical-mechanical polishing

KELLOG CO

Multi-piece fruit snack

Multi-piece fruit snack

NEOPAD TECHNOLOGIES CORP

Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs

MASSACHUSETTS INST TECHNOLOGY

Microphotonic waveguide including core/cladding interface layer

APV BAKER INC

Baked corn-based product and process

GEN FOODS INC

Process for making simulated fruit pieces

TOKYO ELECTRON LTD

Silicon germanium surface layer for high-k dielectric integration