Inventor
MEI SHAW-NING
US13 patents
Patents
13 patentsUS6130453AOct 10, 2000
Flash memory structure with floating gate in vertical trench
IBM150 citations97
US5521399AMay 28, 1996
Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit
IBM24 citations92
US5484738AJan 16, 1996
Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits
IBM34 citations92
US5394294AFeb 28, 1995
Self protective decoupling capacitor structure
IBM38 citations92
US5331199AJul 19, 1994
Bipolar transistor with reduced topography
IBM28 citations91
US5446312AAug 29, 1995
Vertical-gate CMOS compatible lateral bipolar transistor
IBM19 citations80
US6541349B2Apr 1, 2003
Shallow trench isolation using non-conformal dielectric and planarizatrion
IBM18 citations79
US6270353B1Aug 7, 2001
Low cost shallow trench isolation using non-conformal dielectric material
IBM16 citations79
US5279987AJan 18, 1994
Fabricating planar complementary patterned subcollectors with silicon epitaxial layer
IBM10 citations73
US5229322AJul 20, 1993
Method of making low resistance substrate or buried layer contact
IBM13 citations72
US5371022ADec 6, 1994
Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor
IBM11 citations71
US6531265B2Mar 11, 2003
Method to planarize semiconductor surface
IBM9 citations68
US5341023AAug 23, 1994
Novel vertical-gate CMOS compatible lateral bipolar transistor
IBM2 citations62