Inventor
BERGEMONT ALBERT M
US19 patents
Patents
19 patentsUS5789791AAug 4, 1998
Multi-finger MOS transistor with reduced gate resistance
NAT SEMICONDUCTOR CORP82 citations96
US5721170AFeb 24, 1998
Method of making a high-voltage MOS transistor with increased breakdown voltage
NAT SEMICONDUCTOR CORP20 citations92
US5455790AOct 3, 1995
High density EEPROM cell array which can selectively erase each byte of data in each row of the array
NAT SEMICONDUCTOR CORP29 citations92
US5436478AJul 25, 1995
Fast access AMG EPROM with segment select transistors which have an increased width
NAT SEMICONDUCTOR CORP37 citations92
US5409854AApr 25, 1995
Method for forming a virtual-ground flash EPROM array with floating gates that are self aligned to the field oxide regions of the array
NAT SEMICONDUCTOR CORP21 citations92
US5304503AApr 19, 1994
Self-aligned stacked gate EPROM cell using tantalum oxide control gate dielectric
NAT SEMICONDUCTOR CORP32 citations92
US5240870AAug 31, 1993
Stacked gate process flow for cross-point EPROM with internal access transistor
NAT SEMICONDUCTOR CORP21 citations92
US5212541AMay 18, 1993
Contactless, 5v, high speed eprom/flash eprom array utilizing cells programmed using source side injection
NAT SEMICONDUCTOR CORP52 citations92
US5496754AMar 5, 1996
Method for preventing bit line-to-bit line leakage in the access transistor region of an AMG EPROM
NAT SEMICONDUCTOR CORP11 citations74
US5604141AFeb 18, 1997
Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction
NAT SEMICONDUCTOR CORP6 citations73
US5589412ADec 31, 1996
Method of making increased-density flash EPROM that utilizes a series of planarized, self-aligned, intermediate strips of conductive material to contact the drain regions
NAT SEMICONDUCTOR CORP17 citations73
US5460990AOct 24, 1995
Method for fabricating a segmented AMG EPROM where only every fourth bit line contacts a select transistor in a row of segment select transistors
NAT SEMICONDUCTOR CORP6 citations73
US5453393ASep 26, 1995
Method for forming a high density EEPROM cell array with improved access time
NAT SEMICONDUCTOR CORP12 citations73
US5402372AMar 28, 1995
High density EEPROM cell array with improved access time and method of manufacture
NAT SEMICONDUCTOR CORP5 citations73
US5371030ADec 6, 1994
Method of fabricating field oxide isolation for a contactless flash EPROM cell array
NAT SEMICONDUCTOR CORP18 citations73
US5091327AFeb 25, 1992
Fabrication of a high density stacked gate eprom split cell with bit line reach-through and interruption immunity
NAT SEMICONDUCTOR CORP15 citations73
US5086410AFeb 4, 1992
Non-erasable eprom cell for redundancy circuit
NAT SEMICONDUCTOR CORP15 citations73
US5604698AFeb 18, 1997
Virtual-ground flash EPROM array with reduced cell pitch in the X direction
NAT SEMICONDUCTOR CORP4 citations62
US6184099B1Feb 6, 2001
Low cost deep sub-micron CMOS process
NAT SEMICONDUCTOR CORP6 citations54