Inventor
WHITE STEVEN WAYNE
US27 patents
⚠️ This page may combine multiple inventors who share the name “WHITE STEVEN WAYNE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS8037034B2Oct 11, 2011
Methods of creating a dictionary for data compression
IBM309 citations98
US7283072B1Oct 16, 2007
Methods of creating a dictionary for data compression
IBM190 citations98
US6021485AFeb 1, 2000
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
IBM113 citations98
US5887161AMar 23, 1999
Issuing instructions in a processor supporting out-of-order execution
IBM62 citations96
US5870582AFeb 9, 1999
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched
IBM60 citations96
US6971000B1Nov 29, 2005
Use of software hint for branch prediction in the absence of hint bit in the branch instruction
IBM39 citations93
US6658534B1Dec 2, 2003
Mechanism to reduce instruction cache miss penalties and methods therefor
IBM28 citations92
US6266767B1Jul 24, 2001
Apparatus and method for facilitating out-of-order execution of load instructions
IBM28 citations92
US6098167AAug 1, 2000
Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution
IBM40 citations92
US6070238AMay 30, 2000
Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction
IBM25 citations92
US5931957AAug 3, 1999
Support for out-of-order execution of loads and stores in a processor
IBM57 citations92
US5913048AJun 15, 1999
Dispatching instructions in a processor supporting out-of-order execution
IBM45 citations92
US5870612AFeb 9, 1999
Method and apparatus for condensed history buffer
IBM22 citations92
US5860014AJan 12, 1999
Method and apparatus for improved recovery of processor state using history buffer
IBM21 citations92
US5805849ASep 8, 1998
Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions
IBM36 citations92
US5802571ASep 1, 1998
Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory
IBM44 citations92
US7168070B2Jan 23, 2007
Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer
IBM27 citations89
US6021467AFeb 1, 2000
Apparatus and method for processing multiple cache misses to a single cache line
IBM13 citations74
US5864341AJan 26, 1999
Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding
IBM15 citations72
US5784604AJul 21, 1998
Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging
IBM11 citations72
US6079002AJun 20, 2000
Dynamic expansion of execution pipeline stages
IBM9 citations71
US6167500ADec 26, 2000
Mechanism for queuing store data and method therefor
IBM1 citations52
US7530063B2May 5, 2009
Method and system for code modification based on cache structure
IBM1 citations50
OLSZEWSKI BRET RONALD
3 patentsUS8195879B2Jun 5, 2012
Demand based partitioning of microprocessor caches
OLSZEWSKI BRET RONALD5 citations73
US8458401B2Jun 4, 2013
Demand based partitioning of microprocessor caches
OLSZEWSKI BRET RONALD0 citations51
US8447929B2May 21, 2013
Demand based partitioning of microprocessor caches
OLSZEWSKI BRET RONALD1 citations51