Inventor

MAY CATHY

US38 patents

⚠️ This page may combine multiple inventors who share the name “MAY CATHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAY CATHY

IBM

Hypervisor-enforced isolation of entities within a single logical partition&#39;s virtual address space

Efficient enforcement of barriers with respect to memory move sequences

Translation entry invalidation in a multithreaded data processing system

Data stream prefetching in a microprocessor

Apparatus and method for selectively invalidating entries in an address translation cache

Data stream prefetching in a microprocessor

Hardware based isolation for secure execution of virtual machines

Translation entry invalidation in a multithreaded data processing system

Interaction of transactional storage accesses with other atomic semantics

Mechanism for avoiding check stops in speculative accesses while operating in real mode

Mechanism for avoiding check stops in speculative accesses while operating in real mode

Limiting concurrent modification and execution of instructions to a particular type to avoid unexpected results

Method and apparatus for selecting the architecture level to which a processor appears to conform

Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor

Interruptible translation entry invalidation in a multithreaded data processing system

Selectively invalidating entries in an address translation cache

Rewind only transactions in a data processing system supporting transactional storage accesses

Translation load instruction with access protection

Efficient enforcement of barriers with respect to memory move sequences

Memory move instruction sequence including a stream of copy-type and paste-type instructions

Transaction check instruction for memory transactions

Transaction check instruction for memory transactions

Determining failure context in hardware transactional memories

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses

Conditional transaction abort and precise abort handling

ARNDT RICHARD L

Transactional memory preemption mechanism

Transactional memory preemption mechanism

BRUCE BECKY

Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition

Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

FREY BRADLY G

Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses

Specifying an access hint for prefetching limited use data in a cache hierarchy

MOTOROLA INC

Data processing system for processing vector data and method therefor

FREY BRADLY GEORGE

Specifying an access hint for prefetching partial cache block data in a cache hierarchy

CAIN III HAROLD W

Transactional memory system supporting unbroken suspended execution

BLAINEY ROBERT J

Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

CAIN HAROLD W

Apparatus for determining failure context in hardware transactional memories

CHADHA SUNDEEP

Multiple page size segment encoding

Hypervisor-enforced isolation of entities within a single logical partition's virtual address space