Inventor
ANDREEV ALEXANDRE
US17 patents
⚠️ This page may combine multiple inventors who share the name “ANDREEV ALEXANDRE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI CORP
7 patentsUS7389484B2Jun 17, 2008
Method and apparatus for tiling memories in integrated circuit layout
LSI CORP10 citations83
US7424687B2Sep 9, 2008
Method and apparatus for mapping design memories to integrated circuit layout
LSI CORP6 citations73
US8046643B2Oct 25, 2011
Transport subsystem for an MBIST chain architecture
LSI CORP2 citations62
US8037432B2Oct 11, 2011
Method and apparatus for mapping design memories to integrated circuit layout
LSI CORP3 citations62
US7584442B2Sep 1, 2009
Method and apparatus for generating memory models and timing database
LSI CORP3 citations62
US7949909B2May 24, 2011
Address controlling in the MBIST chain architecture
LSI CORP1 citations51
US7308633B2Dec 11, 2007
Master controller architecture
LSI CORP0 citations41
LSI LOGIC CORP
4 patentsUS7093228B2Aug 15, 2006
Method and system for classifying an integrated circuit for optical proximity correction
LSI LOGIC CORP221 citations98
US7200826B2Apr 3, 2007
RRAM memory timing learning tool
LSI LOGIC CORP9 citations73
US7155688B2Dec 26, 2006
Memory generation and placement
LSI LOGIC CORP1 citations51
US7207026B2Apr 17, 2007
Memory tiling architecture
LSI LOGIC CORP0 citations41
ANDREEV ALEXANDRE
4 patentsUS8156391B2Apr 10, 2012
Data controlling in the MBIST chain architecture
ANDREEV ALEXANDRE8 citations82
US8245168B2Aug 14, 2012
Method and apparatus for generating memory models and timing database
ANDREEV ALEXANDRE2 citations61
US8566769B2Oct 22, 2013
Method and apparatus for generating memory models and timing database
ANDREEV ALEXANDRE0 citations50
US8209589B2Jun 26, 2012
Reed-solomon decoder with a variable number of correctable errors
ANDREEV ALEXANDRE1 citations45