Inventor
HUISINGA TORSTEN
DE19 patents
⚠️ This page may combine multiple inventors who share the name “HUISINGA TORSTEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
8 patentsUS9305878B2Apr 5, 2016
Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
GLOBALFOUNDRIES INC2 citations62
US8932911B2Jan 13, 2015
Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
GLOBALFOUNDRIES INC2 citations62
US7985668B1Jul 26, 2011
Method for forming a metal silicide having a lower potential for containing material defects
GLOBALFOUNDRIES INC6 citations62
US8383510B2Feb 26, 2013
Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
GLOBALFOUNDRIES INC2 citations61
US9257329B2Feb 9, 2016
Methods for fabricating integrated circuits including densifying interlevel dielectric layers
GLOBALFOUNDRIES INC2 citations56
US9685497B2Jun 20, 2017
Embedded metal-insulator-metal capacitor
GLOBALFOUNDRIES INC0 citations51
US9478602B2Oct 25, 2016
Method of forming an embedded metal-insulator-metal (MIM) capacitor
GLOBALFOUNDRIES INC0 citations51
US9287109B2Mar 15, 2016
Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
GLOBALFOUNDRIES INC0 citations40
HUISINGA TORSTEN
5 patentsUS8399335B2Mar 19, 2013
Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features
HUISINGA TORSTEN9 citations82
US8598714B2Dec 3, 2013
Semiconductor device comprising through hole vias having a stress relaxation mechanism
HUISINGA TORSTEN11 citations81
US8786088B2Jul 22, 2014
Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
HUISINGA TORSTEN4 citations72
US8859418B2Oct 14, 2014
Methods of forming conductive structures using a dual metal hard mask technique
HUISINGA TORSTEN2 citations60
US8673770B2Mar 18, 2014
Methods of forming conductive structures in dielectric layers on an integrated circuit device
HUISINGA TORSTEN0 citations49
RICHTER RALF
3 patentsUS8216928B1Jul 10, 2012
Methods for fabricating semiconductor devices having local contacts
RICHTER RALF4 citations62
US8324108B2Dec 4, 2012
Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry
RICHTER RALF0 citations52
US8435841B2May 7, 2013
Enhancement of ultraviolet curing of tensile stress liner using reflective materials
RICHTER RALF1 citations51
HEINRICH JENS
2 patentsUS8492269B2Jul 23, 2013
Hybrid contact structure with low aspect ratio contacts in a semiconductor device
HEINRICH JENS2 citations62
US8922023B2Dec 30, 2014
Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
HEINRICH JENS0 citations37