Inventor
O'MEARA DAVID L
US36 patents
⚠️ This page may combine multiple inventors who share the name “O'MEARA DAVID L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOKYO ELECTRON LTD
18 patentsUS9443731B1Sep 13, 2016
Material processing to achieve sub-10nm patterning
TOKYO ELECTRON LTD21 citations91
US9831099B2Nov 28, 2017
Method and apparatus for multi-film deposition and etching in a batch processing system
TOKYO ELECTRON LTD8 citations84
US9171736B2Oct 27, 2015
Spacer material modification to improve K-value and etch properties
TOKYO ELECTRON LTD16 citations83
US7509962B2Mar 31, 2009
Method and control system for treating a hafnium-based dielectric processing system
TOKYO ELECTRON LTD7 citations71
US10580650B2Mar 3, 2020
Method for bottom-up formation of a film in a recessed feature
TOKYO ELECTRON LTD1 citations62
US7470591B2Dec 30, 2008
Method of forming a gate stack containing a gate dielectric layer having reduced metal content
TOKYO ELECTRON LTD4 citations60
US7501352B2Mar 10, 2009
Method and system for forming an oxynitride layer
TOKYO ELECTRON LTD3 citations58
US7479454B2Jan 20, 2009
Method and processing system for monitoring status of system components
TOKYO ELECTRON LTD3 citations57
US11567407B2Jan 31, 2023
Method for globally adjusting spacer critical dimension using photo-active self-assembled monolayer
TOKYO ELECTRON LTD0 citations52
US11417526B2Aug 16, 2022
Multiple patterning processes
TOKYO ELECTRON LTD0 citations52
US10734228B2Aug 4, 2020
Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes
TOKYO ELECTRON LTD0 citations52
US10079151B2Sep 18, 2018
Method for bottom-up deposition of a film in a recessed feature
TOKYO ELECTRON LTD0 citations52
US11532517B2Dec 20, 2022
Localized etch stop layer
TOKYO ELECTRON LTD0 citations51
US10700009B2Jun 30, 2020
Ruthenium metal feature fill for interconnects
TOKYO ELECTRON LTD0 citations51
US12598932B2Apr 7, 2026
Methods and structures for improving etch profile of underlying layers
TOKYO ELECTRON LTD0 citations50
US7141765B2Nov 28, 2006
Heat treating device
TOKYO ELECTRON LTD1 citations49
US12451354B2Oct 21, 2025
Double patterning method of patterning a substrate
TOKYO ELECTRON LTD0 citations48
US12400872B2Aug 26, 2025
Sacrificial capping layer for gate protection
TOKYO ELECTRON LTD0 citations47
MOTOROLA INC
6 patentsUS6297095B1Oct 2, 2001
Memory device that includes passivated nanoclusters and method for manufacture
MOTOROLA INC284 citations99
US6362071B1Mar 26, 2002
Method for forming a semiconductor device with an opening in a dielectric layer
MOTOROLA INC149 citations98
US6320784B1Nov 20, 2001
Memory cell and method for programming thereof
MOTOROLA INC180 citations98
US6344403B1Feb 5, 2002
Memory device and method for manufacture
MOTOROLA INC142 citations96
US6686633B1Feb 3, 2004
Semiconductor device, memory cell, and processes for forming them
MOTOROLA INC16 citations91
US6184073B1Feb 6, 2001
Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region
MOTOROLA INC27 citations91
O'MEARA DAVID L
4 patentsUS8673725B2Mar 18, 2014
Multilayer sidewall spacer for seam protection of a patterned structure
O'MEARA DAVID L15 citations83
US8809169B2Aug 19, 2014
Multi-layer pattern for alternate ALD processes
O'MEARA DAVID L6 citations72
US8460945B2Jun 11, 2013
Method for monitoring status of system components
O'MEARA DAVID L2 citations56
US8664102B2Mar 4, 2014
Dual sidewall spacer for seam protection of a patterned structure
O'MEARA DAVID L1 citations51
IBM
3 patentsUS6974779B2Dec 13, 2005
Interfacial oxidation process for high-k gate dielectric process integration
IBM20 citations91
US7235440B2Jun 26, 2007
Formation of ultra-thin oxide layers by self-limiting interfacial oxidation
IBM5 citations59
US7202186B2Apr 10, 2007
Method of forming uniform ultra-thin oxynitride layers
IBM1 citations49