Inventor

KO AKITERU

US58 patents

⚠️ This page may combine multiple inventors who share the name “KO AKITERU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KO AKITERU

TOKYO ELECTRON LTD

Organic mandrel protection process

Method for etching high-K dielectric using pulsed bias power

Method for etching high-K dielectric using pulsed bias power

Method for etching high-K dielectric using pulsed bias power

Method for increasing pattern density in self-aligned patterning integration schemes

Method for increasing pattern density in self-aligned patterning schemes without using hard masks

Material processing to achieve sub-10nm patterning

Method for patterning differing critical dimensions at sub-resolution scales

Method for etching silicon-containing ARC layer with reduced CD bias

Method and system for capping of cores for self-aligned multiple patterning

Wrap-around contact integration scheme

Method for modifying spacer profile

Mitigation of asymmetrical profile in self aligned patterning etch

Method and system for sculpting spacer sidewall mask

Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables

Etch process for reducing directed self assembly pattern defectivity

Direct current superposition curing for resist reflow temperature enhancement

Process and system for etching doped silicon using SF6-based chemistry

Oblique deposition and etch processes

Methods to reduce microbridge defects in EUV patterning for microelectronic workpieces

Methods to reshape spacer profiles in self-aligned multiple patterning

Forming a semiconductor feature using atomic layer etch

Plasma treatment method to improve photo resist roughness and remove photo resist scum

Sidewall image transfer method for low aspect ratio patterns

Methods to reduce gouging for core removal processes using thermal decomposition materials

Methods to reshape spacers for multi-patterning processes using thermal decomposition materials

Method of patterning low-k materials using thermal decomposition materials

Cyclic method for reactive development of photoresists

Etch process for reducing directed self assembly pattern defectivity using direct current positioning

Method and system for forming a feature in a high-k layer

Metal oxide resists for EUV patterning and methods for developing the same

Reduced contaminant gas injection system and method of using

Surface fluorination remediation for aluminium oxide electrostatic chucks

Method for pitch split patterning using sidewall image transfer

Substrate processing method using multiline patterning

Multiple patterning processes

Method of line cut by multi-color patterning technique

Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes

Methods for EUV inverse patterning in processing of microelectronic workpieces

Method and process using dual memorization layer for multi-color spacer patterning

Method and process for forming memory hole patterns

Method to transfer patterns to a layer

Method and system for etching a high-k dielectric material

Acid for reactive development of metal oxide resists

LUONG VINH HOANG

Etch process for controlling pattern CD and integrity in multi-layer masks

Differential metal gate etching process

KO AKITERU

Etch process for reducing silicon recess

Method for etching metal nitride with high selectivity to other materials

RANJAN ALOK

Method for etching high-k dielectric using pulsed bias power

COLE CHRISTOPHER

Method for patterning an ARC layer using SF6 and a hydrocarbon gas