Inventor

KERBER PRANITA

US94 patents

⚠️ This page may combine multiple inventors who share the name “KERBER PRANITA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KERBER PRANITA

IBM

Reduced resistance SiGe FinFET devices and method of forming same

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

SiGe FinFET with improved junction doping control

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Structure and method for highly strained germanium channel fins for high mobility pFINFETs

Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same

SiGe FinFET with improved junction doping control

Defect reduction with rotated double aspect ratio trapping

FinFET device with vertical silicide on recessed source/drain epitaxy regions

MOSFET with recessed channel film and abrupt junctions

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same

Semiconductor device having SSOI substrate with relaxed tensile stress

SOI device with DTI and STI

Controlled fin-merging for fin type FET devices

Field effect transistor with asymmetric abrupt junction implant

Reduced resistance SiGe FinFET devices and method of forming same

High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

Asymmetric III-V MOSFET on silicon substrate

Metallized junction FinFET structures

Semiconductor device including epitaxially formed buried channel region

Selective importance sampling

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Asymmetric III-V MOSFET on silicon substrate

Semiconductor device including gate channel having adjusted threshold voltage

Reduced resistance short-channel InGaAs planar MOSFET

Reduced current leakage semiconductor device

SiGe finFET with improved junction doping control

Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

Method and structure to enhance gate induced strain effect in multigate device

Non-uniform gate dielectric for U-shape MOSFET

III-V transistor device with self-aligned doped bottom barrier

High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Reduced current leakage semiconductor device

Semiconductor device including epitaxially formed buried channel region

Semiconductor device including gate channel having adjusted threshold voltage

Semiconductor device including gate channel having adjusted threshold voltage

Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same

Integrated circuit diode

MOSFET with recessed channel film and abrupt junctions

GLOBALFOUNDRIES INC

FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same

MOSFET with work function adjusted metal backgate

Junction field effect transistor with an epitaxially grown gate structure

FinFET device having a merge source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same

Shallow trench isolation structures

III-V MOSFETs with halo-doped bottom barrier layer

MOSFET with work function adjusted metal backgate