Inventor

OUYANG QIQING C

US55 patents

⚠️ This page may combine multiple inventors who share the name “OUYANG QIQING C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OUYANG QIQING C

IBM

Reduced resistance SiGe FinFET devices and method of forming same

Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body

Quasi self-aligned source/drain FinFET process

Integrated microfluidics system

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

High performance strained silicon FinFETs device and method for forming same

Vertical MOSFET with dual work function materials

Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate

SiGe FinFET with improved junction doping control

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Structure and method for highly strained germanium channel fins for high mobility pFINFETs

SiGe FinFET with improved junction doping control

FinFET device with vertical silicide on recessed source/drain epitaxy regions

FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same

Method of reducing detrimental STI-induced stress in MOSFET channels

Super hybrid SOI CMOS devices

Structure for and method of fabricating a high-mobility field-effect transistor

Mandrel/trim alignment in SIT processing

High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same

Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof

Structure for and method of fabricating a high-mobility field-effect transistor

Semiconductor device including epitaxially formed buried channel region

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Semiconductor device including gate channel having adjusted threshold voltage

Reduced resistance short-channel InGaAs planar MOSFET

SiGe finFET with improved junction doping control

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Semiconductor device including epitaxially formed buried channel region

Semiconductor device including gate channel having adjusted threshold voltage

Semiconductor device including gate channel having adjusted threshold voltage

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification

Stressed field effect transistors on hybrid orientation substrate

Method of forming CMOS with Si:C source/drain by laser melting and recrystallization

Method of forming a MOSFET with dual work function materials

High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same

Higher performance CMOS on (110) wafers

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Semiconductor device including epitaxially formed buried channel region

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Reduced resistance short-channel InGaAs planar MOSFET

Semiconductor device including epitaxially formed buried channel region

GLOBALFOUNDRIES INC

Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flow

FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same

FinFET device having a merge source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same

Transistor structure with varied gate cross-sectional area

Transistor structure with varied gate cross-sectional area

DENNARD ROBERT H

Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels

GEBARA FADI H

Embedded photodetector apparatus in a 3D CMOS chip stack

RENESAS ELECTRONICS CORP

Semiconductor device and method of manufacturing the semiconductor device