Inventor

SCHEPIS DOMINIC J

US133 patents

⚠️ This page may combine multiple inventors who share the name “SCHEPIS DOMINIC J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHEPIS DOMINIC J

IBM

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device

Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

Thermal conductivity enhanced semiconductor structures and fabrication processes

Sige channel epitaxial development for high-k PFET manufacturability

Method of forming a body contact using BOX modification

MOS transistors with raised sources and drains

Process of fabricating planar and densely patterned silicon-on-insulator structure

Antifuse element with electrical or optical programming

Electrically programmable antifuse using metal penetration of a junction

BiCMOS process

Method of making defect free silicon islands using SEG

Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture

Process of etching an oxide layer

Double diamond shaped unmerged epitaxy for tall fins in tight pitch

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet

SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer

Densely patterned silicon-on-insulator (SOI) region on a wafer

Thermal conductivity enhanced semiconductor structures and fabrication processes

Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET

Method of making a self cooling electrically programmable fuse

Method of forming a thermally activated noise immune fuse

Self cooling electrically programmable fuse

Thermally activated noise immune fuse

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings

Semiconductor device having a strained raised source/drain

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

Field effect transistor with stressed channel and method for making same

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

Silicon-on-insulator chip having an isolation barrier for reliability

Method of integrating substrate contact on SOI wafers with STI process

Method for forming notch gate having self-aligned raised source/drain structure

Surface engineering to prevent EPI growth on gate poly during selective EPI processing

Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability

Self protective decoupling capacitor structure

Method of making semiconductor device contact including transition metal-compound dopant source

Total dielectric isolation for integrated circuits

Total dielectric isolation for integrated circuits

Fully amorphized source/drain for leaky junctions

Method for forming an antifuse element with electrical or optical programming

Low dielectric constant sidewall spacer using notch gate process

FinFET having highly doped source and drain regions

Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

GLOBALFOUNDRIES INC

Contact formation for stacked FinFETs

Implant-free punch through doping layer formation for bulk FinFET structures

Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing