Inventor

YIP AARON S

US38 patents

⚠️ This page may combine multiple inventors who share the name “YIP AARON S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YIP AARON S

MICRON TECHNOLOGY INC

Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly under the staircase

Memory cell programming utilizing conditional enabling of memory cells

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Microelectronic devices, electronic systems having a memory array region and a control logic region, and methods of forming microelectronic devices

Block-on-block memory array architecture using bi-directional staircases

Memory devices with four data line bias levels

Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells

Vertical string driver for memory array

Block-on-block memory array architecture using bi-directional staircases

Memory cell programming

Memory devices with user-defined tagging mechanism

Apparatuses and methods for generating probabilistic information with current integration sensing

Apparatuses and methods for generating probabilistic information with current integration sensing

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

Sub-block definition in a memory device using segmented source plates

Block-on-block memory array architecture using bi-directional staircases

Using non-segregated cells as drain-side select gates for sub-blocks in a memory device

Microelectronic devices including control logic regions

Microelectronic devices having a memory array region, a control logic region, and signal routing structures

Memory devices with user-defined tagging mechanism

Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

Apparatus for memory cell programming

Memory cell programming applying a programming pulse having different voltage levels

Microelectronic devices and memory devices

Memories for decoding memory access addresses for access operations

Memory cell programming with a program pulse having a plurality of different voltage levels

Memory devices with four data line bias levels

Apparatus and methods for decoding memory access addresses for access operations

Memory cell programming with a programming pulse having plurality of different voltage levels

Erasing memory cells

Erasing memory cells sequentially

Access line management in a memory device

Memory cell programming using VgVt value

Access line management in a memory device

Access line management in a memory device

Access line management in a memory device

Independent plane architecture in a memory device

CYPRESS SEMICONDUCTOR CORP

Architecture for FPGAs