Inventor

HSU FU-CHANG

US131 patents

⚠️ This page may combine multiple inventors who share the name “HSU FU-CHANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU FU-CHANG

APLUS FLASH TECHNOLOGY INC

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Parallel channel programming scheme for MLC flash memory

Charge pump circuits

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device

Set of three level concurrent word line bias conditions for a nor type flash memory array

Three step write process used for a nonvolatile NOR type EEPROM memory

Positive/negative high voltage charge pump system

Node-precise voltage regulation for a MOS memory system

3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Flash memory array structure suitable for multiple simultaneous operations

Reversed split-gate cell array

Node-precise voltage regulation for a MOS memory system

Bias condition and X-decoder circuit of flash memory array

Flash memory with high speed erasing structure using thin oxide semiconductor devices

Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

Approach to provide high external voltage for flash memory erase

Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Flash memory array structure suitable for multiple simultaneous operations

Highly-integrated flash memory and mask ROM array architecture

Stacked gate flash memory cell with reduced disturb conditions

Flash memory array for multiple simultaneous operations

Flash memory array structure suitable for multiple simultaneous operations

Multiple level flash memory

Reversed split-gate cell array

Bias conditions for repair, program and erase operations of non-volatile memory

Erase condition for flash memory

Flash memory with novel bitline decoder and sourceline latch

Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices

APLUS INTEGRATED CIRCUITS INC

Flash memory wordline decoder with overerase repair

Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array

Flash memory protection attribute status bits held in a flash memory array

Memory device with on-chip manufacturing and memory cell defect detection capability

Flash memory read/write controller

Flash memory with row redundancy

Flash EEPROM worldline decoder

LEE PETER WUNG

NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same

High speed high density nand-based 2T-NOR flash memory design

Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array