Inventor

CHEN DE-FANG

TW58 patents

⚠️ This page may combine multiple inventors who share the name “CHEN DE-FANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN DE-FANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming an integrated circuit using a patterned mask layer

Vertical device having a protrusion source

Method of forming an integrated circuit using a patterned mask layer

Tunnel field-effect transistor

Method of forming an integrated circuit using a patterned mask layer

Self-aligned nanowire formation using double patterning

Nano wire structure and method for fabricating the same

Vertical device having a protrusion source

Method of forming an integrated circuit using a patterned mask layer

Self-aligned nanowire formation using double patterning

Vertical device having a protrusion structure

Methods for improved critical dimension uniformity in a semiconductor device fabrication process

Methods for fabricating vertical-gate-all-around transistor structures

Lithographic technique incorporating varied pattern materials

Method of making a silicide beneath a vertical structure

Vertical structure having an etch stop over portion of the source

Method of forming channel of gate structure

Nano wire structure and method for fabricating the same

Vertical-gate-all-around devices and method of fabrication thereof

Self-aligned multiple spacer patterning process

Vertical device having a protrusion source

Self-aligned nanowire formation using double patterning

Nano wire structure and method for fabricating the same

Method of forming an integrated circuit using a patterned mask layer

Method for improved critical dimension uniformity in a semiconductor device fabrication process

Structure and formation method of semiconductor device with nanosheet structure

Method for improved critical dimension uniformity in a semiconductor device fabrication process

Method of forming isolation layer

Semiconductor device with multiple threshold voltage and method of fabricating the same

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor devices with modified source/drain feature and methods thereof

Semiconductor devices with modified source/drain feature and methods thereof

Method of forming isolation layer

Self-aligned nanowire formation using double patterning

Method of forming isolation layer

Semiconductor device and method of forming vertical structure

Lithographic technique incorporating varied pattern materials

Gate structure

Semiconductor device with multiple threshold voltage and method of fabricating the same

Methods for improved critical dimension uniformity in a semiconductor device fabrication process

Semiconductor device and method of forming vertical structure

Tunnel field-effect transistor

Nano wire structure and method for fabricating the same

TAIWAN SEMICONDUCTOR MFG

Method of forming a vertical device

Method of reducing a critical dimension of a semiconductor device

Semiconductor device and method of forming vertical structure

Method of forming an integrated circuit using a patterned mask layer

Multi-line width pattern created using photolithography

HSIEH TZU-YEN

Method of forming an integrated circuit