Inventor
DRAPER ANDREW
GB31 patents
⚠️ This page may combine multiple inventors who share the name “DRAPER ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
21 patentsUS7822958B1Oct 26, 2010
Booting mechanism for FPGA-based embedded system
ALTERA CORP49 citations97
US7350178B1Mar 25, 2008
Embedded processor with watchdog timer for programmable logic
ALTERA CORP61 citations97
US7340596B1Mar 4, 2008
Embedded processor with watchdog timer for programmable logic
ALTERA CORP101 citations97
US6826717B1Nov 30, 2004
Synchronization of hardware and software debuggers
ALTERA CORP124 citations97
US7546424B1Jun 9, 2009
Embedded processor with dual-port SRAM for programmable logic
ALTERA CORP14 citations92
US7096324B1Aug 22, 2006
Embedded processor with dual-port SRAM for programmable logic
ALTERA CORP34 citations92
US7078929B1Jul 18, 2006
Interface controller using JTAG scan chain
ALTERA CORP22 citations92
US6732263B1May 4, 2004
Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
ALTERA CORP39 citations92
US6862724B1Mar 1, 2005
Reconfigurable programmable logic system with peripheral identification data
ALTERA CORP24 citations88
US7321996B1Jan 22, 2008
Digital data error insertion methods and apparatus
ALTERA CORP9 citations83
US7249222B1Jul 24, 2007
Prefetching data based on predetermined criteria
ALTERA CORP16 citations83
US6828822B1Dec 7, 2004
Apparatus and methods for shared memory interfaces in programmable logic devices
ALTERA CORP18 citations79
US9404968B1Aug 2, 2016
System and methods for debug connectivity discovery
ALTERA CORP3 citations73
US7343483B1Mar 11, 2008
Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream
ALTERA CORP8 citations73
US6937061B1Aug 30, 2005
Address decoder for programmable logic device
ALTERA CORP7 citations72
US7412624B1Aug 12, 2008
Methods and apparatus for debugging a system with a hung data bus
ALTERA CORP4 citations63
US7657689B1Feb 2, 2010
Methods and apparatus for handling reset events in a bus bridge
ALTERA CORP6 citations62
US7584348B1Sep 1, 2009
Techniques for configuring an embedded processor operating system
ALTERA CORP2 citations60
US7263623B1Aug 28, 2007
Microprocessor system
ALTERA CORP5 citations58
US7549004B1Jun 16, 2009
Split filtering in multilayer systems
ALTERA CORP6 citations54
US7064578B1Jun 20, 2006
Distributed bus structure
ALTERA CORP0 citations37