Inventor

GRIEBENOW UWE

DE45 patents

⚠️ This page may combine multiple inventors who share the name “GRIEBENOW UWE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRIEBENOW UWE

GRIEBENOW UWE

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

Optical signal transfer in a semiconductor device by using monolithic opto-electronic components

Semiconductor device comprising a buried waveguide for device internal optical communication

Method for increasing penetration depth of drain and source implantation species for a given gate height

Stress transfer enhancement in transistors by a late gate re-crystallization

Reduced silicon thickness of N-channel transistors in SOI CMOS devices

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Semiconductor device comprising a stacked die configuration including an integrated Peltier element

Method for increasing penetration depth of drain and source implantation species for a given gate height

HOENTSCHEL JAN

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices

Strain memorization in strained SOI substrates of semiconductor devices

In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile

Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions

Stress adjustment in stressed dielectric materials of semiconductor devices by stress relaxation based on radiation

GLOBALFOUNDRIES INC

Technique for enhancing transistor performance by transistor specific contact design

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

Transistor having a high-k metal gate stack and a compressively stressed channel

Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region

Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions

Semiconductor device comprising a stacked die configuration including an integrated peltier element

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Method for adjusting the height of a gate electrode in a semiconductor device

ADVANCED MICRO DEVICES INC

Drive current increase in transistors by asymmetric amorphization implantation

Recessed drain and source areas in combination with advanced silicide formation in transistors

Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region

High-K gate electrode structure formed after transistor fabrication by using a spacer

Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor device

SCHEIPER THILO

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Contact bars with reduced fringing capacitance in a semiconductor device

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

Field effect transistors for a flash memory comprising a self-aligned charge storage region

BEYER SVEN

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

FROHBERG KAI

High-K gate electrode structure formed after transistor fabrication by using a spacer

Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach

GERHARDT MARTIN

Technique for enhancing transistor performance by transistor specific contact design