Inventor

RUTTLOFF KERSTIN

DE12 patents

⚠️ This page may combine multiple inventors who share the name “RUTTLOFF KERSTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLOBALFOUNDRIES INC

3 patents

US7981740B2Jul 19, 2011

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

GLOBALFOUNDRIES INC13 citations82

US8039338B2Oct 18, 2011

Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction

GLOBALFOUNDRIES INC1 citations52

US8048726B2Nov 1, 2011

SOI semiconductor device with reduced topography above a substrate window area

GLOBALFOUNDRIES INC0 citations51

GRIEBENOW UWE

2 patents

US8110487B2Feb 7, 2012

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

GRIEBENOW UWE104 citations97

US8440534B2May 14, 2013

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

GRIEBENOW UWE2 citations61

BEYER SVEN

1 patent

US8318598B2Nov 27, 2012

Contacts and vias of a semiconductor device formed by a hard mask and double exposure

BEYER SVEN6 citations72

SCHEIPER THILO

1 patent

US8709902B2Apr 29, 2014

Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure

SCHEIPER THILO2 citations62

WIECZOREK KARSTEN

1 patent

US8097542B2Jan 17, 2012

Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors

WIECZOREK KARSTEN2 citations56

HEINRICH JENS

1 patent

US8436425B2May 7, 2013

SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure

HEINRICH JENS1 citations51

HORSTMANN MANFRED

1 patent

US8188871B2May 29, 2012

Drive current adjustment for transistors by local gate engineering

HORSTMANN MANFRED0 citations45

KRONHOLZ STEPHAN

1 patent

US8772843B2Jul 8, 2014

Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices

KRONHOLZ STEPHAN0 citations39

LENSKI MARKUS

1 patent

US8987103B2Mar 24, 2015

Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device

LENSKI MARKUS0 citations36