Inventor
KUDVA PRABHAKAR N
US22 patents
⚠️ This page may combine multiple inventors who share the name “KUDVA PRABHAKAR N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS7723207B2May 25, 2010
Three dimensional integrated circuit and method of design
IBM277 citations99
US7312487B2Dec 25, 2007
Three dimensional integrated circuit
IBM335 citations99
US7421601B2Sep 2, 2008
Method and system for controlling power in a chip through a power-performance monitor and control unit
IBM73 citations98
US7065665B2Jun 20, 2006
Interlocked synchronous pipeline clock gating
IBM45 citations96
US7685457B2Mar 23, 2010
Interlocked synchronous pipeline clock gating
IBM12 citations92
US6946869B2Sep 20, 2005
Method and structure for short range leakage control in pipelined circuits
IBM31 citations92
US7076681B2Jul 11, 2006
Processor with demand-driven clock throttling power reduction
IBM31 citations91
US7308593B2Dec 11, 2007
Interlocked synchronous pipeline clock gating
IBM10 citations84
US7100144B2Aug 29, 2006
System and method for topology selection to minimize leakage power during synthesis
IBM14 citations84
US7930578B2Apr 19, 2011
Method and system of peak power enforcement via autonomous token-based control and management
IBM17 citations83
US7475227B2Jan 6, 2009
Method of stalling one or more stages in an interlocked synchronous pipeline
IBM5 citations74
US6608771B2Aug 19, 2003
Low-power circuit structures and methods for content addressable memories and random access memories
IBM9 citations73
US6512397B1Jan 28, 2003
Circuit structures and methods for high-speed low-power select arbitration
IBM12 citations73
US6314547B1Nov 6, 2001
Method for improving the assignment of circuit locations during fabrication
IBM12 citations73
US7801835B2Sep 21, 2010
Method for constructing autonomic advisors and learning procedural knowledge from scored examples
IBM6 citations62
US7373615B2May 13, 2008
Method for optimization of logic circuits for routability
IBM5 citations59
US7676779B2Mar 9, 2010
Logic block timing estimation using conesize
IBM2 citations57
BOSE PRADIP
4 patentsUS8112642B2Feb 7, 2012
Method and system for controlling power in a chip through a power-performance monitor and control unit
BOSE PRADIP14 citations92
US8639955B2Jan 28, 2014
Method and system for controlling power in a chip through a power performance monitor and control unit
BOSE PRADIP8 citations84
US8091050B2Jan 3, 2012
Modeling system-level effects of soft errors
BOSE PRADIP7 citations84
US8949101B2Feb 3, 2015
Hardware execution driven application level derating calculation for soft error rate analysis
BOSE PRADIP14 citations82