Inventor

ZHAI JUN

US108 patents

⚠️ This page may combine multiple inventors who share the name “ZHAI JUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHAI JUN

APPLE INC

Independent 3D stacking

System in package fan out stacking architecture and process flow

Integrated MEMS microphone and vibration sensor

Systems and methods for forming die sets with die-to-die routing and metallic seals

High density interconnection using fanout interposer chiplet

Three layer stack structure

Dual molded stack TSV package

Double side mounting memory integration in thin low warpage fanout package

Three layer stack structure

Fan out system in package and method for forming the same

Package with SoC and integrated memory

Structure and method for fabricating a computing system with an integrated voltage regulator module

3D integration of fanout wafer level packages

Die stitching and harvesting of arrayed structures

High bandwidth die to die interconnect with package area reduction

Die-to-die routing through a seal ring

High density 3D interconnect configuration

Power management system switched capacitor voltage regulator with integrated passive device

High bandwidth die to die interconnect with package area reduction

Package with SoC and integrated memory

SOC with integrated voltage regulator using preformed MIM capacitor wafer

Biometric sensor chip having distributed sensor and control circuitry

Package with SoC and integrated memory

Biometric sensor chip having distributed sensor and control circuitry

PoP structure with electrically insulating material between packages

Wearable electronic device with fluid-based pressure sensing

Integrated circuit die decoupling system with reduced inductance

EMI shielded wafer level fan-out pop package

High bandwidth die to die interconnect with package area reduction

High density interconnection using fanout interposer chiplet

Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability

Interconnecting dies by stitch routing

Wafer reconstitution and die-stitching

High density interconnection using fanout interposer chiplet

Fully interconnected heterogeneous multi-layer reconstructed silicon device

Wafer reconstitution and die-stitching

Trimmable banked capacitor

Multi-die fine grain integrated voltage regulation

3D fanout stacking

Structure and method for fabricating a computing system with an integrated voltage regulator module

Multi-die fine grain integrated voltage regulation

3D thin profile pre-stacking architecture using reconstitution method

Stacked wafer DDR package

Dual-sided silicon integrated passive devices

ADVANCED MICRO DEVICES INC

Integrated circuit package and method

Semiconductor chip with stratified underfill

Interconnects with improved electromigration reliability

GLOBALFOUNDRIES INC

Semiconductor chip with crack stop

TOSAYA ERIC

Chip package with channel stiffener frame

HE WENBIN

Expression builder