Inventor

HU KUNZHONG

US62 patents

⚠️ This page may combine multiple inventors who share the name “HU KUNZHONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU KUNZHONG

APPLE INC

Independent 3D stacking

System in package fan out stacking architecture and process flow

High density interconnection using fanout interposer chiplet

Three layer stack structure

Dual molded stack TSV package

Double side mounting memory integration in thin low warpage fanout package

Three layer stack structure

Systems and methods for implementing a scalable system

Systems and methods for implementing a scalable system

Structure and method for fabricating a computing system with an integrated voltage regulator module

3D integration of fanout wafer level packages

Die stitching and harvesting of arrayed structures

High bandwidth die to die interconnect with package area reduction

High density 3D interconnect configuration

High bandwidth die to die interconnect with package area reduction

SOC with integrated voltage regulator using preformed MIM capacitor wafer

High bandwidth die to die interconnect with package area reduction

High density interconnection using fanout interposer chiplet

Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability

Wafer reconstitution and die-stitching

High density interconnection using fanout interposer chiplet

Wafer reconstitution and die-stitching

3D fanout stacking

Structure and method for fabricating a computing system with an integrated voltage regulator module

3D thin profile pre-stacking architecture using reconstitution method

Dual-sided silicon integrated passive devices

SOC with integrated voltage regulator using preformed MIM capacitor wafer

Very fine pitch and wiring density organic side by side chiplet integration

Selectable monolithic or external scalable die-to-die interconnection system methodology

High density 3D interconnect configuration

Selectable monolithic or external scalable die-to-die interconnection system methodology

Systems and methods for implementing a scalable system

Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring

Die stitching and harvesting of arrayed structures

Structure and method for fabricating a computing system with an integrated voltage regulator module

Wafer reconstitution and die-stitching

High density 3D interconnect configuration

Structure and method for fabricating a computing system with an integrated voltage regulator module

INT RECTIFIER CORP

Multi-chip module

High current lead electrode for semiconductor device

Semiconductor package

Semiconductor package with conductive heat spreader

Package for monolithic compound semiconductor (CSC) devices for DC to DC converters

Interdigitated conductive lead frame or laminate lead frame for GaN die

Copper straps

Cascoded rectifier package

HU KUNZHONG

Semiconductor package with metal straps

Wafer level package resistance monitor scheme

INFINEON TECHNOLOGIES AMERICAS CORP

Semiconductor package with heat spreader

BRIERE MICHAEL A

Semiconductor package