Inventor

MERTEN MATTHEW C

US44 patents

⚠️ This page may combine multiple inventors who share the name “MERTEN MATTHEW C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MERTEN MATTHEW C

INTEL CORP

Method and apparatus for speculative execution of uncontended lock instructions

Predicting contention in a processor

Method and apparatus to prevent voltage droop in a computer

Method and apparatus for processor performance monitoring

Virtualizing precise event based sampling

Virtualizing precise event based sampling

Providing status of a processing device with periodic synchronization point in instruction tracing system

Cooperative triggering

Addition instructions with independent carry chains

Technique for using memory attributes

Virtualizing precise event based sampling

Trace management during aborted speculative operations

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Compare and exchange operation using sleep-wakeup mechanism

Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit

Method and apparatus for obtaining a call stack to an event of interest and analyzing the same

Method and apparatus for continued retirement during commit of a speculative region of code

Two level re-order buffer

Technique for using memory attributes

Minimizing bandwith to compress output stream in instruction tracing systems

Method and apparatus for implementing dynamic portbinding within a reservation station

Method and apparatus for implementing dynamic portbinding within a reservation station

Physical reference list for tracking physical register sharing

SRINIVASAN SRIKANTH T

Scheduler implementing dependency matrix having restricted entries

Instruction and logic for non-blocking register reclamation

IMPACT TECHNOLOGIES INC

Method and apparatus for modulo scheduled loop execution in a processor architecture

GOPAL VINODH

Addition instructions with independent carry chains

CAPRIOLI PAUL

Hardware profiling mechanism to enable page level automatic binary translation

STRONG BEEMAN C

Minimizing bandwidth to track return targets by an instruction tracing system

KADGI VIJAYKUMAR B

Systems and methods for flag tracking in move elimination operations

KNAUTH LAURA A

SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combination

HWU WEN-MEI W

Method and apparatus for modulo scheduled loop execution in a processor architecture

MERTEN MATTHEW C

Enhanced loop streaming detector to drive logic optimization

RAJWAR RAVI

Instruction and logic to test transactional execution status

SAHA BRATIN

Compare and exchange operation using sleep-wakeup mechanism

JACOBSON QUINN A

Technique for using memory attributes

SURYANARAYANAN ANUPAMA

Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuit

CHYNOWETH MICHAEL W

Method and apparatus for obtaining a call stack to an event of interest and analyzing the same

JOURDAN STEPHAN J

Forward-pass dead instruction identification and removal at run-time