Inventor

BRANDT JASON W

US134 patents

⚠️ This page may combine multiple inventors who share the name “BRANDT JASON W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRANDT JASON W

INTEL CORP

Maintaining processor resources during architectural events

Cryptographic computing using encrypted base addresses and used in multi-tenant environments

Protection of keys and sensitive data from attack within microprocessor architecture

Processor extensions to protect stacks during ring transitions

Dynamically partitioning pipeline resources

Encoded inline capabilities

Associating address space identifiers with active contexts

Control transfer termination instructions of an instruction set architecture (ISA)

Processor extensions to protect stacks during ring transitions

Binding of cryptographic operations to context or speculative execution restrictions

Processor extensions to protect stacks during ring transitions

Apparatuses, methods, and systems for instructions to compartmentalize code

Keyed-hash message authentication code processors, methods, systems, and instructions

Cryptographic computing using encrypted base addresses and used in multi-tenant environments

Maintaining processor resources during architectural events

Attack protection for valid gadget control transfers

Hardware apparatuses and methods to switch shadow stack pointers

Maintaining processor resources during architectural events

Hardware enforced one-way cryptography

Loading and virtualizing cryptographic keys

Attack Protection for valid gadget control transfers

Monitoring performance of a processor using reloadable performance counters

Control transfer termination instructions of an instruction set architecture (ISA)

Real time instruction trace processors, methods, and systems

Defining virtualized page attributes based on guest page attributes

Zeroing a cache line

Sequencer address management

Method and apparatus for processor performance monitoring

Maintaining processor resources during architectural events

Maintaining processor resources during architectural events

Apparatus, system, and method for persistent user-level thread

Maintaining processor resources during architectural events

Processor extensions to protect stacks during ring transitions

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Protection of keys and sensitive data from attack within microprocessor architecture

Mode-specific endbranch for control flow termination

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Mode-specific endbranch for control flow termination

Control transfer termination instructions of an instruction set architecture (ISA)

Systems and methods for protecting symmetric encryption keys

Return address overflow buffer

Instruction-set support for invocation of VMM-configured services without VMM intervention

HUGHES CHRISTOPHER J

Gathering and scattering multiple data elements

NEIGER GILBERT

Method and apparatus for a guest to access a privileged register

GROBMAN STEVEN L

Systems and methods for protecting symmetric encryption keys

CHINYA GAUTHAM

Apparatus, system, and method for persistent user-level thread

STRONG BEEMAN C

Managing generated trace data for a virtual machine

SODHI INDER M

Execution context swap between heterogeneous functional hardware units

COX GEORGE W

Method and apparatus for a non-deterministic random bit generator (NRBG)