Inventor
RUBIN JOSHUA M
US75 patents
Patents
50 patentsUS10607938B1Mar 31, 2020
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
IBM50 citations98
US10103065B1Oct 16, 2018
Gate metal patterning for tight pitch applications
IBM50 citations98
US9954058B1Apr 24, 2018
Self-aligned air gap spacer for nanosheet CMOS devices
IBM79 citations98
US11164817B2Nov 2, 2021
Multi-chip package structures with discrete redistribution layers
IBM32 citations94
US11101318B2Aug 24, 2021
Back-side memory element with local memory select transistor
IBM14 citations94
US11094637B2Aug 17, 2021
Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
IBM17 citations94
US10243043B2Mar 26, 2019
Self-aligned air gap spacer for nanosheet CMOS devices
IBM16 citations94
US9711501B1Jul 18, 2017
Interlayer via
IBM34 citations94
US10748901B2Aug 18, 2020
Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
IBM11 citations86
US10692768B1Jun 23, 2020
Vertical transport field-effect transistor architecture
IBM13 citations86
US10636791B1Apr 28, 2020
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
IBM5 citations84
US10593681B1Mar 17, 2020
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple
IBM9 citations84
US10483344B1Nov 19, 2019
Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
IBM8 citations84
US10461148B1Oct 29, 2019
Multilayer buried metal-insultor-metal capacitor structures
IBM10 citations84
US10446606B2Oct 15, 2019
Back-side memory element with local memory select transistor
IBM13 citations84
US9786546B1Oct 10, 2017
Bulk to silicon on insulator device
IBM7 citations84
US9761498B2Sep 12, 2017
Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
IBM6 citations84
US9735062B1Aug 15, 2017
Defect reduction in channel silicon germanium on patterned silicon
IBM9 citations84
US9634113B2Apr 25, 2017
Fully silicided linerless middle-of-line (MOL) contact
IBM7 citations84
US9570590B1Feb 14, 2017
Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
IBM6 citations84
US10714420B1Jul 14, 2020
High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations
IBM7 citations82
US11574875B2Feb 7, 2023
Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
IBM2 citations73
US11164791B2Nov 2, 2021
Contact formation for stacked vertical transport field-effect transistors
IBM3 citations73
US11133259B2Sep 28, 2021
Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network
IBM4 citations73
US11069679B2Jul 20, 2021
Reducing gate resistance in stacked vertical transport field effect transistors
IBM4 citations73
US11049844B2Jun 29, 2021
Semiconductor wafer having trenches with varied dimensions for multi-chip modules
IBM3 citations73
US10910312B2Feb 2, 2021
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
IBM2 citations73
US10903165B2Jan 26, 2021
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
IBM2 citations73
US10833081B2Nov 10, 2020
Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET)
IBM2 citations73
US10770460B2Sep 8, 2020
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
IBM2 citations73
US10755985B2Aug 25, 2020
Gate metal patterning for tight pitch applications
IBM4 citations73
US10700067B2Jun 30, 2020
Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices
IBM3 citations73
US10600694B2Mar 24, 2020
Gate metal patterning for tight pitch applications
IBM4 citations73
US10121877B1Nov 6, 2018
Vertical field effect transistor with metallic bottom region
IBM3 citations73
US9997607B2Jun 12, 2018
Mirrored contact CMOS with self-aligned source, drain, and back-gate
IBM2 citations73
US9978871B2May 22, 2018
Bulk to silicon on insulator device
IBM2 citations73
US9881925B2Jan 30, 2018
Mirror contact capacitor
IBM2 citations73
US9853151B2Dec 26, 2017
Fully silicided linerless middle-of-line (MOL) contact
IBM3 citations73
US9627410B2Apr 18, 2017
Metallized junction FinFET structures
IBM3 citations73
US10991635B2Apr 27, 2021
Multiple chip bridge connector
IBM2 citations72
US9812571B2Nov 7, 2017
Tensile strained high percentage silicon germanium alloy FinFETs
IBM3 citations71
US12364004B2Jul 15, 2025
Dummy fin contact in vertically stacked transistors
IBM0 citations63
US12167612B2Dec 10, 2024
Back-side memory element with local memory select transistor
IBM0 citations63
US11855191B2Dec 26, 2023
Vertical FET with contact to gate above active fin
IBM0 citations63
US11756957B2Sep 12, 2023
Reducing gate resistance in stacked vertical transport field effect transistors
IBM0 citations63
US11563003B2Jan 24, 2023
Fin top hard mask formation after wafer flipping process
IBM1 citations63
US10971504B2Apr 6, 2021
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple
IBM1 citations63
US10903307B2Jan 26, 2021
Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
IBM1 citations63
US10147815B2Dec 4, 2018
Fully silicided linerless middle-of-line (MOL) contact
IBM1 citations63
US9991339B2Jun 5, 2018
Bulk to silicon on insulator device
IBM1 citations63
Showing the top 50 of 75 patents by PatentIndex Score.