Inventor

PRANATHARTHIHARAN BALASUBRAMANIAN

US199 patents

⚠️ This page may combine multiple inventors who share the name “PRANATHARTHIHARAN BALASUBRAMANIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRANATHARTHIHARAN BALASUBRAMANIAN

IBM

Confined phase change memory with double air gap

Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices

Method for forming merged contact for semiconductor device

Method of forming contact useful in replacement metal gate processing and related semiconductor structure

Bi-layer gate cap for self-aligned contact formation

Trench silicide contacts with high selectivity process

Minimizing shorting between FinFET epitaxial regions

Minimizing shorting between FinFET epitaxial regions

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Low resistance replacement metal gate structure

Gate contact with vertical isolation from source-drain

Nanosheet bottom isolation and source or drain epitaxial growth

Replacement contact formation for gate contact over active region with selective metal growth

Patterning method for nanosheet transistors

Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

FinFETs with various fin height

Dual liner silicide

Minimizing shorting between FinFET epitaxial regions

Gate contact with vertical isolation from source-drain

Method and structure of improving contact resistance for passive and long channel devices

Strained CMOS on strain relaxation buffer substrate

Nanosheet isolation for bulk CMOS non-planar devices

Strained CMOS on strain relaxation buffer substrate

Minimizing shorting between FinFET epitaxial regions

Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture

Self-aligned local interconnect technology

Fin type field effect transistors with different pitches and substantially uniform fin reveal

Stable contact on one-sided gate tie-down structure

Minimize middle-of-line contact line shorts

Forming dual contact silicide using metal multi-layer and ion beam mixing

Method to prevent lateral epitaxial growth in semiconductor devices

Solid state diffusion doping for bulk finFET devices

Semiconductor devices with sidewall spacers of equal thickness

Parasitic capacitance reduction

Self heating reduction for analog radio frequency (RF) device

Semiconductor devices with sidewall spacers of equal thickness

Confined eptaxial growth for continued pitch scaling

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Gate contact with vertical isolation from source-drain

Integrated multiple gate length semiconductor device including self-aligned contacts

Halo region formation by epitaxial growth

Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)

Method for forming self-aligned metal silicide contacts

Method for forming self-aligned metal silicide contacts

GLOBALFOUNDRIES INC

FinFET spacer formation on gate sidewalls, between the channel and source/drain regions

Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices

Contact formation for ultra-scaled devices

Methods of forming a semiconductor device with a protected gate cap layer and the resulting device

XIE RUILONG

Methods of forming semiconductor devices with self-aligned contacts and the resulting devices

CHANG JOSEPHINE

Preventing shorting of adjacent devices