Inventor

DUSAD SHAGUN

IN48 patents

⚠️ This page may combine multiple inventors who share the name “DUSAD SHAGUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUSAD SHAGUN

TEXAS INSTRUMENTS INC

Delay-based residue stage

Delay-based residue stage

Conversion and folding circuit for delay-based analog-to-digital converter system

Time gain compensation

Time-dependant gain control for an amplifier used in receiving echoes

Calibration technique for current steering DAC

Apparatus having source follower based DAC inter-symbol interference cancellation

Bias removal in PRBS based channel estimation

Transceiver with in-phase and quadrature-phase coupling correction

Transceiver with in-phase and quadrature-phase coupling correction

Negative capacitance circuits including temperature-compensation biasings

Delay modulated clock division

Time gain compensation circuit in an ultrasound receiver

Current-based track and hold circuit

Time gain compensation circuit in an ultrasound receiver

Counter-based SYSREF implementation

Delta sigma modulator with dynamic error cancellation

Pattern based estimation of errors in ADC

Feedforward cancellation of power supply noise in a voltage regulator

Clock filter with negative resistor circuit

Conversion and folding circuit for delay-based analog-to-digital converter system

Gain and memory error estimation in a pipeline analog to digital converter

Clock filter with negative resistor circuit

Conversion and folding circuit for delay-based analog-to-digital converter system

Delay-based residue stage

Bias removal in PRBS based channel estimation

Gain and memory error estimation in a pipeline analog to digital converter

Continuous time linear capacitive digital step attenuator

Calibration scheme for filling lookup table in an ADC

Gain correction for multi-bit successive-approximation register

Multibit recyclic pipelined ADC architecture

Lookup table for non-linear systems

Current-based track and hold circuit

Counter-based SYSREF implementation

Balun with improved common mode rejection ratio

Balun with improved common mode rejection ratio

Circuits for improving linearity of metal oxide semiconductor (MOS) transistors

Switched capacitor gain stage

Multi-bit voltage-to-delay conversion in data converter circuitry

Gain correction for multi-bit successive-approximation register

Dynamic integrator with boosted output impedance of the transconductance

Delta sigma modulator with dynamic error cancellation

Pattern based estimation of errors in ADC

Low parasitic capacitor array

Top plate sampling analog-to-digital converter (ADC) with residue amplifier non-linearity reduction

DUSAD SHAGUN

Amplifier circuits with reduced power consumption

NIMRAN P A VAJEED

Cancellation of products generated by harmonics of a square wave used in square-wave mixing

WALA SHABBIR AMJHERA

Ultrasonic receiver front-end