Inventor
CHAN YUEN HUNG
US19 patents
⚠️ This page may combine multiple inventors who share the name “CHAN YUEN HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS5783949AJul 21, 1998
Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
IBM23 citations92
US10367507B2Jul 30, 2019
Dynamic decode circuit with active glitch control
IBM3 citations83
US9966958B2May 8, 2018
Dynamic decode circuit with active glitch control
IBM8 citations83
US9742408B1Aug 22, 2017
Dynamic decode circuit with active glitch control
IBM8 citations83
US6105109AAug 15, 2000
System speed loading of a writable cache code array
IBM11 citations73
US5740412AApr 14, 1998
Set-select multiplexer with an array built-in self-test feature
IBM8 citations72
US7167385B2Jan 23, 2007
Method and apparatus for controlling the timing of precharge in a content addressable memory system
IBM9 citations70
US7936198B2May 3, 2011
Progamable control clock circuit for arrays
IBM4 citations63
US7813189B2Oct 12, 2010
Array data input latch and data clocking scheme
IBM3 citations61
US9537474B2Jan 3, 2017
Transforming a phase-locked-loop generated chip clock signal to a local clock signal
IBM0 citations52
US9401698B1Jul 26, 2016
Transforming a phase-locked-loop generated chip clock signal to a local clock signal
IBM1 citations52
US10320388B2Jun 11, 2019
Dynamic decode circuit with active glitch control method
IBM0 citations51
US10312916B2Jun 4, 2019
Dynamic decode circuit with delayed precharge
IBM0 citations51
US10312915B2Jun 4, 2019
Dynamic decode circuit with active glitch control method
IBM0 citations51
US10224933B2Mar 5, 2019
Dynamic decode circuit with active glitch control
IBM0 citations51
US7099201B1Aug 29, 2006
Multifunctional latch circuit for use with both SRAM array and self test device
IBM1 citations49
US8837235B1Sep 16, 2014
Local evaluation circuit for static random-access memory
IBM0 citations40