Inventor
SHRIVASTAVA RITU
US25 patents
⚠️ This page may combine multiple inventors who share the name “SHRIVASTAVA RITU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALLIANCE SEMICONDUCTOR CORP
15 patentsUS5518942AMay 21, 1996
Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
ALLIANCE SEMICONDUCTOR CORP109 citations98
US5994730ANov 30, 1999
DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
ALLIANCE SEMICONDUCTOR CORP50 citations96
US5416738AMay 16, 1995
Single transistor flash EPROM cell and method of operation
ALLIANCE SEMICONDUCTOR CORP78 citations96
US6258714B1Jul 10, 2001
Self-aligned contacts for salicided MOS devices
ALLIANCE SEMICONDUCTOR CORP24 citations92
US6166409ADec 26, 2000
Flash EPROM memory cell having increased capacitive coupling
ALLIANCE SEMICONDUCTOR CORP23 citations92
US6392267B1May 21, 2002
Flash EPROM array with self-aligned source contacts and programmable sector erase architecture
ALLIANCE SEMICONDUCTOR CORP15 citations84
US5856944AJan 5, 1999
Self-converging over-erase repair method for flash EPROM
ALLIANCE SEMICONDUCTOR CORP18 citations82
US6472267B2Oct 29, 2002
DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
ALLIANCE SEMICONDUCTOR CORP5 citations74
US6373089B1Apr 16, 2002
DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
ALLIANCE SEMICONDUCTOR CORP7 citations74
US6133602AOct 17, 2000
Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures
ALLIANCE SEMICONDUCTOR CORP14 citations74
US6020237AFeb 1, 2000
Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures
ALLIANCE SEMICONDUCTOR CORP5 citations74
US5701264ADec 23, 1997
Dynamic random access memory cell having increased capacitance
ALLIANCE SEMICONDUCTOR CORP17 citations74
US6429076B2Aug 6, 2002
Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereof
ALLIANCE SEMICONDUCTOR CORP10 citations73
US6589834B1Jul 8, 2003
Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
ALLIANCE SEMICONDUCTOR CORP2 citations63
US5672535ASep 30, 1997
Method of fabricating DRAM cell with self-aligned contact
ALLIANCE SEMICONDUCTOR CORP3 citations54
ZETTACORE INC
3 patentsUS7358113B2Apr 15, 2008
Processing systems and methods for molecular memory
ZETTACORE INC12 citations81
US7642546B2Jan 5, 2010
Molecular memory devices including solid-state dielectric layers and related methods
ZETTACORE INC5 citations62
US7799598B2Sep 21, 2010
Processing systems and methods for molecular memory
ZETTACORE INC4 citations60