Inventor
KLOSTER GRANT
US24 patents
⚠️ This page may combine multiple inventors who share the name “KLOSTER GRANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS6905958B2Jun 14, 2005
Protecting metal conductors with sacrificial organic monolayers
INTEL CORP52 citations96
US6867125B2Mar 15, 2005
Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
INTEL CORP54 citations96
US7214594B2May 8, 2007
Method of making semiconductor device using a novel interconnect cladding layer
INTEL CORP19 citations92
US7122481B2Oct 17, 2006
Sealing porous dielectrics with silane coupling reagents
INTEL CORP15 citations92
US7335586B2Feb 26, 2008
Sealing porous dielectric material using plasma-induced surface polymerization
INTEL CORP12 citations84
US7456490B2Nov 25, 2008
Sealing porous dielectrics with silane coupling reagents
INTEL CORP9 citations83
US6964919B2Nov 15, 2005
Low-k dielectric film with good mechanical strength
INTEL CORP13 citations82
US7354862B2Apr 8, 2008
Thin passivation layer on 3D devices
INTEL CORP9 citations79
US7217595B2May 15, 2007
Sealed three dimensional metal bonded integrated circuits
INTEL CORP7 citations74
US7030040B2Apr 18, 2006
Selectively growing a polymeric material on a semiconductor substrate
INTEL CORP6 citations74
US10243080B2Mar 26, 2019
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
INTEL CORP3 citations73
US7186637B2Mar 6, 2007
Method of bonding semiconductor devices
INTEL CORP7 citations73
US6867473B2Mar 15, 2005
Plating a conductive material on a dielectric material
INTEL CORP6 citations73
US6682989B1Jan 27, 2004
Plating a conductive material on a dielectric material
INTEL CORP12 citations73
US7164206B2Jan 16, 2007
Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
INTEL CORP8 citations70
US7658975B2Feb 9, 2010
Sealing porous dielectric materials
INTEL CORP2 citations63
US12165987B2Dec 10, 2024
Frame reveals with maskless lithography in the manufacture of integrated circuits
INTEL CORP0 citations62
US12381161B2Aug 5, 2025
Backside wafer treatments to reduce distortions and overlay errors during wafer chucking
INTEL CORP0 citations61
US7214605B2May 8, 2007
Deposition of diffusion barrier
INTEL CORP6 citations60
US7145245B2Dec 5, 2006
Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate—therein
INTEL CORP4 citations60
US7560165B2Jul 14, 2009
Sealing porous dielectric materials
INTEL CORP2 citations59
US10756215B2Aug 25, 2020
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
INTEL CORP0 citations52
US7422020B2Sep 9, 2008
Aluminum incorporation in porous dielectric for improved mechanical properties of patterned dielectric
INTEL CORP1 citations49