Inventor
CLENDENNING SCOTT B
US48 patents
⚠️ This page may combine multiple inventors who share the name “CLENDENNING SCOTT B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
40 patentsUS9932671B2Apr 3, 2018
Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD)
INTEL CORP10 citations84
US9793061B2Oct 17, 2017
Energy storage device, method of manufacturing same, and mobile electronic device containing same
INTEL CORP5 citations84
US9530733B2Dec 27, 2016
Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment of the layers over adjacent regions
INTEL CORP8 citations84
US11264449B2Mar 1, 2022
Capacitor architectures in semiconductor devices
INTEL CORP5 citations83
US10497613B2Dec 3, 2019
Microelectronic conductive routes and methods of making the same
INTEL CORP5 citations73
US10243080B2Mar 26, 2019
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
INTEL CORP3 citations73
US9818847B2Nov 14, 2017
Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
INTEL CORP3 citations73
US9455150B2Sep 27, 2016
Conformal thin film deposition of electropositive metal alloy films
INTEL CORP3 citations73
US10971600B2Apr 6, 2021
Selective gate spacers for semiconductor devices
INTEL CORP1 citations72
US10720508B2Jul 21, 2020
Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
INTEL CORP3 citations72
US10396176B2Aug 27, 2019
Selective gate spacers for semiconductor devices
INTEL CORP3 citations72
US11869889B2Jan 9, 2024
Self-aligned gate endcap (SAGE) architectures without fin end gap
INTEL CORP4 citations71
US9786559B2Oct 10, 2017
Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias (TSVs)
INTEL CORP3 citations69
US12396254B2Aug 19, 2025
Stacked 2D CMOS with inter metal layers
INTEL CORP1 citations63
US11672133B2Jun 6, 2023
Vertically stacked memory elements with air gap
INTEL CORP1 citations62
US11594485B2Feb 28, 2023
Local interconnect with air gap
INTEL CORP0 citations62
US11532724B2Dec 20, 2022
Selective gate spacers for semiconductor devices
INTEL CORP0 citations62
US10998423B2May 4, 2021
Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
INTEL CORP0 citations62
US10886175B2Jan 5, 2021
Differentiated molecular domains for selective hardmask fabrication and structures resulting therefrom
INTEL CORP0 citations62
US10658487B2May 19, 2020
Semiconductor devices having ruthenium phosphorus thin films
INTEL CORP1 citations62
US9390932B2Jul 12, 2016
Electropositive metal containing layers for semiconductor applications
INTEL CORP2 citations62
US9090964B2Jul 28, 2015
Additives to improve the performance of a precursor source for cobalt deposition
INTEL CORP2 citations62
US12369382B2Jul 22, 2025
Integrated circuit structures with graphene contacts
INTEL CORP0 citations61
US12342551B2Jun 24, 2025
Capacitor architectures in semiconductor devices
INTEL CORP0 citations61
US11901404B2Feb 13, 2024
Capacitor architectures in semiconductor devices
INTEL CORP0 citations61
US11791375B2Oct 17, 2023
Capacitor architectures in semiconductor devices
INTEL CORP0 citations61
US12588257B2Mar 24, 2026
2D layered gate oxide
INTEL CORP0 citations60
US11270887B2Mar 8, 2022
Passivation layer for germanium substrate
INTEL CORP0 citations60
US11217456B2Jan 4, 2022
Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication
INTEL CORP0 citations60
US11923290B2Mar 5, 2024
Halogen treatment for NMOS contact resistance improvement
INTEL CORP0 citations59
US10896852B2Jan 19, 2021
Methods for doping a sub-fin region of a semiconductor fin structure and devices containing the same
INTEL CORP0 citations59
US12575165B2Mar 10, 2026
Transistor devices with high-k perovskite gate dielectrics
INTEL CORP0 citations57
US12595276B2Apr 7, 2026
Mid-valent molybdenum complexes for thin film deposition
INTEL CORP0 citations56
US11227798B2Jan 18, 2022
Metal aluminum gallium indium carbide thin films as liners and barriers for interconnects
INTEL CORP0 citations52
US10756215B2Aug 25, 2020
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
INTEL CORP0 citations52
US12500162B2Dec 16, 2025
Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition
INTEL CORP0 citations50
US10777366B2Sep 15, 2020
Method of increasing an energy density and an achievable power output of an energy storage device
INTEL CORP0 citations50
US12598977B2Apr 7, 2026
Fill of vias in single and dual damascene structures using self-assembled monolayer
INTEL CORP0 citations49
US12183739B2Dec 31, 2024
Ribbon or wire transistor stack with selective dipole threshold voltage shifter
INTEL CORP0 citations47
US9928966B2Mar 27, 2018
Nanostructured electrolytic energy storage devices
INTEL CORP0 citations41
ROMERO PATRICIO E
3 patentsUS9236292B2Jan 12, 2016
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
ROMERO PATRICIO E125 citations98
US9583389B2Feb 28, 2017
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
ROMERO PATRICIO E7 citations83
US8952355B2Feb 10, 2015
Electropositive metal containing layers for semiconductor applications
ROMERO PATRICIO E2 citations61