Inventor

LIAO SZUYA S

US50 patents

Patents

50 patents

US9882027B2Jan 30, 2018

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

INTEL CORP12 citations93

US9831306B2Nov 28, 2017

Self-aligned gate edge and local interconnect and method to fabricate same

INTEL CORP29 citations93

US11056492B1Jul 6, 2021

Dense memory arrays utilizing access transistors with back-side contacts

INTEL CORP9 citations85

US10461177B2Oct 29, 2019

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

INTEL CORP4 citations84

US10319812B2Jun 11, 2019

Self-aligned gate edge and local interconnect and method to fabricate same

INTEL CORP9 citations83

US11640988B2May 2, 2023

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

INTEL CORP2 citations73

US11127841B2Sep 21, 2021

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

INTEL CORP3 citations73

US10896963B2Jan 19, 2021

Semiconductor device contacts with increased contact area

INTEL CORP2 citations73

US10453967B2Oct 22, 2019

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

INTEL CORP3 citations73

US10243080B2Mar 26, 2019

Selective deposition utilizing sacrificial blocking layers for semiconductor devices

INTEL CORP3 citations73

US11217582B2Jan 4, 2022

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

INTEL CORP2 citations72

US10971600B2Apr 6, 2021

Selective gate spacers for semiconductor devices

INTEL CORP1 citations72

US10790354B2Sep 29, 2020

Self-aligned gate edge and local interconnect

INTEL CORP2 citations72

US10720508B2Jul 21, 2020

Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping

INTEL CORP3 citations72

US10396176B2Aug 27, 2019

Selective gate spacers for semiconductor devices

INTEL CORP3 citations72

US11869889B2Jan 9, 2024

Self-aligned gate endcap (SAGE) architectures without fin end gap

INTEL CORP4 citations71

US11183592B2Nov 23, 2021

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

INTEL CORP4 citations71

US11043492B2Jun 22, 2021

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

INTEL CORP0 citations63

US12426299B2Sep 23, 2025

Fin shaping and integrated circuit structures resulting therefrom

INTEL CORP0 citations62

US11901457B2Feb 13, 2024

Fin shaping and integrated circuit structures resulting therefrom

INTEL CORP0 citations62

US11854894B2Dec 26, 2023

Integrated circuit device structures and double-sided electrical testing

INTEL CORP0 citations62

US11688792B2Jun 27, 2023

Dual self-aligned gate endcap (SAGE) architectures

INTEL CORP0 citations62

US11605632B2Mar 14, 2023

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

INTEL CORP0 citations62

US11563081B2Jan 24, 2023

Self-aligned gate edge and local interconnect

INTEL CORP0 citations62

US11532724B2Dec 20, 2022

Selective gate spacers for semiconductor devices

INTEL CORP0 citations62

US11264453B2Mar 1, 2022

Methods of doping fin structures of non-planar transistor devices

INTEL CORP0 citations62

US11222947B2Jan 11, 2022

Methods of doping fin structures of non-planar transistor devices

INTEL CORP0 citations62

US11205708B2Dec 21, 2021

Dual self-aligned gate endcap (SAGE) architectures

INTEL CORP0 citations62

US11152461B2Oct 19, 2021

Semiconductor layer between source/drain regions and gate spacers

INTEL CORP1 citations62

US11011620B2May 18, 2021

Techniques for increasing channel region tensile strain in n-MOS devices

INTEL CORP0 citations62

US10998423B2May 4, 2021

Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping

INTEL CORP0 citations62

US11908940B2Feb 20, 2024

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

INTEL CORP0 citations61

US11581315B2Feb 14, 2023

Self-aligned gate edge trigate and finFET devices

INTEL CORP0 citations61

US12224326B2Feb 11, 2025

Contact architecture for capacitance reduction and satisfactory contact resistance

INTEL CORP0 citations60

US11824097B2Nov 21, 2023

Contact architecture for capacitance reduction and satisfactory contact resistance

INTEL CORP0 citations60

US11282930B2Mar 22, 2022

Contact architecture for capacitance reduction and satisfactory contact resistance

INTEL CORP0 citations60

US12266536B2Apr 1, 2025

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

INTEL CORP0 citations57

US11887860B2Jan 30, 2024

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

INTEL CORP0 citations57

US10756215B2Aug 25, 2020

Selective deposition utilizing sacrificial blocking layers for semiconductor devices

INTEL CORP0 citations52

US12272688B2Apr 8, 2025

Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap

INTEL CORP0 citations51

US11329138B2May 10, 2022

Self-aligned gate endcap (SAGE) architecture having endcap plugs

INTEL CORP0 citations51

US10872960B2Dec 22, 2020

Contact architecture for capacitance reduction and satisfactory contact resistance

INTEL CORP0 citations49

US11456357B2Sep 27, 2022

Self-aligned gate edge architecture with alternate channel material

INTEL CORP0 citations48

US11984506B2May 14, 2024

Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer

INTEL CORP0 citations44

US10770458B2Sep 8, 2020

Nanowire transistor device architectures

INTEL CORP0 citations42

US10410867B2Sep 10, 2019

Confined and scalable helmet

INTEL CORP0 citations39

LIAO SZUYA S

Patents

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Self-aligned gate edge and local interconnect and method to fabricate same

Dense memory arrays utilizing access transistors with back-side contacts

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Self-aligned gate edge and local interconnect and method to fabricate same

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Semiconductor device contacts with increased contact area

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

Selective deposition utilizing sacrificial blocking layers for semiconductor devices

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

Selective gate spacers for semiconductor devices

Self-aligned gate edge and local interconnect

Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping

Selective gate spacers for semiconductor devices

Self-aligned gate endcap (SAGE) architectures without fin end gap

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

Self-aligned gate edge trigate and finFET devices

Transistors employing non-selective deposition of source/drain material

Source or drain structures with high germanium concentration capping layer

Confined epitaxial regions for semiconductor devices

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

Fin shaping and integrated circuit structures resulting therefrom

Fin shaping and integrated circuit structures resulting therefrom

Integrated circuit device structures and double-sided electrical testing

Dual self-aligned gate endcap (SAGE) architectures

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

Self-aligned gate edge and local interconnect

Selective gate spacers for semiconductor devices

Methods of doping fin structures of non-planar transistor devices

Methods of doping fin structures of non-planar transistor devices

Dual self-aligned gate endcap (SAGE) architectures

Semiconductor layer between source/drain regions and gate spacers

Techniques for increasing channel region tensile strain in n-MOS devices

Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping

Field effect transistor with a hybrid gate spacer including a low-k dielectric material

Self-aligned gate edge trigate and finFET devices

Contact architecture for capacitance reduction and satisfactory contact resistance

Contact architecture for capacitance reduction and satisfactory contact resistance

Contact architecture for capacitance reduction and satisfactory contact resistance

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures

Selective deposition utilizing sacrificial blocking layers for semiconductor devices

Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap

Self-aligned gate endcap (SAGE) architecture having endcap plugs

Contact architecture for capacitance reduction and satisfactory contact resistance

Self-aligned gate edge architecture with alternate channel material

Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer

Nanowire transistor device architectures

Confined and scalable helmet