Inventor

SCHROEDER UWE PAUL

US36 patents

⚠️ This page may combine multiple inventors who share the name “SCHROEDER UWE PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHROEDER UWE PAUL

INFINEON TECHNOLOGIES AG

Method and apparatus for aerial image improvement in projection lithography using a phase shifting aperture

Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning

Method of making a contact in a semiconductor device

Method and apparatus for producing rectangular contact holes utilizing side lobe formation

Method for producing quadratic contact holes utilizing side lobe formation

Method for producing square contact holes utilizing side lobe formation

Method for forming a trench in a layer or a layer stack on a semiconductor wafer

Resolution enhancement for alternating phase shift masks

Method for printing contacts on a substrate

Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect

Lithography masks and methods

Effective assist pattern for nested and isolated contacts

Method of making a contact in a semiconductor device

Lithography masks, systems, and manufacturing methods

Mark configuration, wafer with at least one mark configuration and method for the fabrication of at least one mark configuration

Masks and methods of manufacture thereof

Lithographic mask, and method for covering a mask layer

Radio frequency (RF) circuit placement in semiconductor devices

Method of forming isolated features of semiconductor devices

Method of making an integrated circuit, including forming a contact

GLOBALFOUNDRIES INC

Methods, apparatus, and system for using filler cells in design of integrated circuit devices

Methods, apparatus and system for reduction of power consumption in a semiconductor device

Method of forming a gate contact structure and source/drain contact structure for a semiconductor device

Multi-stage pattern recognition in circuit designs

Three-dimensional pattern risk scoring

Method, system and program product for identifying anomalies in integrated circuit design layouts

SCHROEDER UWE PAUL

Electrostatic discharge (ESD) protection circuit placement in semiconductor devices

Lithography masks, systems, and manufacturing methods

Lithography masks, systems, and manufacturing methods

SRAM memory cell having a dogleg shaped gate electrode structure

IBM

Liquid crystalline light-modulating device

Masks and methods of manufacture thereof

Method for patterning a semiconductor wafer

INFINEON TECHNOLOGIES CORP

‘Via first’ dual damascene process for copper metallization

Semiconductor structures and manufacturing methods

SIEMENS AG

Top layer imaging lithography for semiconductor processing