Inventor

MAZUR MARTIN

DE17 patents

⚠️ This page may combine multiple inventors who share the name “MAZUR MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAZUR MARTIN

ADVANCED MICRO DEVICES INC

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

Technique for controlling mechanical stress in a channel region by spacer removal

Method of defining the dimensions of circuit elements by using spacer deposition techniques

Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

Arc layer having a reduced flaking tendency and a method of manufacturing the same

Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process

Advanced process control model incorporating a target offset term

GLOBALFOUNDRIES INC

Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning

Semiconductor device comprising a floating gate flash memory device

Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions

Reticles for use in forming implant masking layers and methods of forming implant masking layers

BAARS PETER

Method of forming self-aligned contacts for a semiconductor device

RICHTER RALF

Cap layer removal in a high-K metal gate stack by using an etch process

HEMPEL KLAUS

High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology

MAZUR MARTIN

Reticles for use in forming implant masking layers and methods of forming implant masking layers

THEES HANS-JUERGEN

Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping