Inventor

LI CHII-HORNG

TW146 patents

⚠️ This page may combine multiple inventors who share the name “LI CHII-HORNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI CHII-HORNG

TAIWAN SEMICONDUCTOR MFG CO LTD

FETS and methods of forming FETs

Contact resistance control in epitaxial structures of finFET

MOS devices having epitaxy regions with reduced facets

Semiconductor device convex source/drain region

Semiconductor device and manufacturing method thereof

Germanium profile for channel strain

Selective etching in the formation of epitaxy regions in MOS devices

MOS devices with non-uniform P-type impurity profile

V-shaped epitaxially formed semiconductor layer

Source and drain stressors with recessed top surfaces

Transistor strain-inducing scheme

FETS and methods of forming FETS

Interfacial layer between fin and source/drain region

FETS and methods of forming FETS

FinFET device and method for fabricating the same

V-shape recess profile for embedded source/drain epitaxy

Wafer susceptor with improved thermal characteristics

Contact resistance control in epitaxial structures of finFET

Method for manufacturing semiconductor structure with enlarged volumes of source-drain regions

Elongated source/drain region structure in finFET device

Semiconductor device and method of forming same

Fin field-effect transistor device and method of forming the same

Method to reduce etch variation using ion implantation

Source and drain stressors with recessed top surfaces

Semiconductor device and manufacturing method thereof

Source and drain stressors with recessed top surfaces

MOS devices having epitaxy regions with reduced facets

Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration

MOS devices having epitaxy regions with reduced facets

Reducing variation by using combination epitaxy growth

Semiconductor device

Semiconductor method and device

FETS and methods of forming FETS

FETs and methods of forming FETs

TAIWAN SEMICONDUCTOR MFG

Structure and method for semiconductor device

MOS device having source and drain regions with embedded germanium-containing diffusion barrier

MOS devices having epitaxy regions with reduced facets

Methods of manufacturing strained semiconductor devices with facets

Method for fabricating a semiconductor device

CHENG YU-HUNG

Selective etching in the formation of epitaxy regions in MOS devices

Reducing variation by using combination epitaxy growth

Strained semiconductor device with facets

Method for fabricating a semiconductor device

Performing enhanced cleaning in the formation of MOS devices

CHEN CHIEN-HAO

Method of fabricating a sealing structure for high-k metal gate

Sealing structure for high-K metal gate

CHUANG HARRY

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

SU LILLY

Semiconductor device and fabrication method thereof

LEE YEN-RU

Semiconductor device and fabrication method thereof

PENG ERIC

Bottle-neck recess in a semiconductor device