Inventor
LIM YEOW KHENG
SG26 patents
⚠️ This page may combine multiple inventors who share the name “LIM YEOW KHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
16 patentsUS6380084B1Apr 30, 2002
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
CHARTERED SEMICONDUCTOR MFG59 citations94
US7094669B2Aug 22, 2006
Structure and method of liner air gap formation
CHARTERED SEMICONDUCTOR MFG46 citations92
US6613652B2Sep 2, 2003
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
CHARTERED SEMICONDUCTOR MFG28 citations92
US6355563B1Mar 12, 2002
Versatile copper-wiring layout design with low-k dielectric integration
CHARTERED SEMICONDUCTOR MFG46 citations92
US6319767B1Nov 20, 2001
Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique
CHARTERED SEMICONDUCTOR MFG50 citations92
US7790617B2Sep 7, 2010
Formation of metal silicide layer over copper interconnect for reliability enhancement
CHARTERED SEMICONDUCTOR MFG11 citations84
US7253097B2Aug 7, 2007
Integrated circuit system using dual damascene process
CHARTERED SEMICONDUCTOR MFG11 citations84
US6468880B1Oct 22, 2002
Method for fabricating complementary silicon on insulator devices using wafer bonding
CHARTERED SEMICONDUCTOR MFG14 citations84
US6849928B2Feb 1, 2005
Dual silicon-on-insulator device wafer die
CHARTERED SEMICONDUCTOR MFG6 citations74
US6432797B1Aug 13, 2002
Simplified method to reduce or eliminate STI oxide divots
CHARTERED SEMICONDUCTOR MFG13 citations74
US6780691B2Aug 24, 2004
Method to fabricate elevated source/drain transistor with large area for silicidation
CHARTERED SEMICONDUCTOR MFG12 citations73
US6518133B1Feb 11, 2003
Method for fabricating a small dimensional gate with elevated source/drain structures
CHARTERED SEMICONDUCTOR MFG8 citations72
US6967156B2Nov 22, 2005
Method to fabricate aligned dual damascene openings
CHARTERED SEMICONDUCTOR MFG3 citations62
US6399471B1Jun 4, 2002
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
CHARTERED SEMICONDUCTOR MFG4 citations62
US6472697B2Oct 29, 2002
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
CHARTERED SEMICONDUCTOR MFG0 citations52
US7372156B2May 13, 2008
Method to fabricate aligned dual damascene openings
CHARTERED SEMICONDUCTOR MFG0 citations51